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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Verification

Specman And The Cadence ESL+TLM News

Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification…

• 2 min read
IEEE 1647 , DAC , Specman , TLM , Verification methodology , Functional Verification , simvision , OVM e , e , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , ESL , AOP , IES-XL

Analog/Custom Design

DesignCon 2010 Call for Papers

Hello, As a member of the technical committee and as the chair member for the Analog…

• less than a min read
DesignCon , Advanced Node , Mixed-Signal , RF design , mixed signal , Custom IC Design

Verification

What is Next for SystemC?

Let your voice be heard at the North American SystemC Users Group interactive Town…

• 1 min read
TLM , System Design and Verification , OSCI , SystemC , high level synthesis , HLS

Verification

The Scoop on Tracking & Validating Formal Assumptions – You Don’t Need to Assume

" Tackling formal assumptions through verification planning " is a recent article…

• less than a min read
funtional verification , ABV , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , Incisive , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV) , Functional Verificatioa , verification

Verification

North American SystemC User's Group Co-Located at DAC 2009

We've been hearing about SystemC for a while. It's a great language! What's it great…

• less than a min read
OSCI , Analysis , SystemC , NASCUG , System Design and Verification

Verification

Write Right OVM Verification Components

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes…

• 4 min read
SystemVerilog , OVM ML , OVM e , OVM SV , OVMWorld

Analog/Custom Design

Things You Didn't Know About Virtuoso: Search Assistant

People say I have strong google-fu . Whether it's finding information on a homework…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

SoC and IP

NAND Forward Price Drops will Slow Significantly

Author's Note and Errata: There were some errors in the forward NAND pricing in the…

• 9 min read

Digital Design

How To: Create a Self-Contained Testcase in Encounter

In the course of performing design work in Encounter, it frequently becomes desireable…

• 2 min read
Digital Implementation forums , How To , testcase , Encounter Digital Implementation System 8.1

RF Engineering

RF Measurement Library: Capturing Circuit Characterization Setups on the Schemat…

Another design approach that Cadence supports that may not be obvious to all users…

• 1 min read
Circuit simulation , RFIC , custom design , RF design , design framework , RF Measurement library

Verification

TLM-Driven Design and Verification Solution

At this week's CDNLive! Japan we made an important press release announcement about…

• 2 min read
TLM-driven design , Calypto , Incisive , System C , TDM , C-to-Silicon , ARM , System Design and Verification

System, PCB, & Package Design 

What's Good About ABIML in PCB SI? It's in SPB16.2!

First - ABIML is an acronym for A lgorithm- B ased I nterconnect M odel L ibrary…

• 3 min read
SI , SPB 16.2 , ABIML , PCB design , Allegro

Verification

Tips on Using e Macros to Raise Abstraction and Facilitate Reuse

[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.] …

• 5 min read
IEEE 1647 , Specman , Functional Verification , tech tips , e , team specman , macros , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Embedded Software Plays an Important Role in Low Power Design

At Cadence, there is a big focus on low power design . In the mobile world, power…

• 3 min read
android , System Design and Verification , Low power verification and analysis , google , power forward , metric-driven verification , Incisive Software Extensions

Verification

Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: …

• 3 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

SoC and IP

Low-Power Memory Subsystems Imperative

The figure below was put forth at the recent Denali MemCon, in a speech by Samsung…

• 6 min read

Verification

AOP Discussion on LinkedIn

Hello All, Last week over in the LinkedIn Design Verification Professionals group…

• 3 min read
Specman , Functional Verification , OVM , e , AOP

Digital Design

Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in…

• 1 min read
Low Power , dual flop , Digital Implementation

Analog/Custom Design

Things You Didn't Know About Virtuoso: The View From Above

A few years ago I bought a wonderful book called "Earth From Above". An amazing French…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Layout Suite L , Virtuoso , VLS L , Custom IC Design
CDNS - Fix Layout Hompage