Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

CRAFTing Your Aero/Defense UVM Testbench the Easy Way

So you want to build an automated testbench for your aero/defense project, eh? Luckily…

• 2 min read
Functional Verification , VWB , online tool , automated testbench , craft

Breakfast Bytes

CES Review: Rain...and Some Consumer Electronics

I have been at the Consumer Electronics Show (CES) all week. For 116 days through…

• 7 min read
Automotive , Consumer Electronics , CES , CES2018 , virtual reality , augmented reality

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (5 of 8)

Efficient Interconnect Extraction Once physical layout is complete, (or at least…

• 3 min read
Serial link analysis , SI , Multi-Gigabit , Interconnect Extraction , IBIS-AMI , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

What's For Breakfast? Video Preview January 15th to 19th 2018

https://youtu.be/MPkAPCQyFvY Coming from Consumer Electronics Show, Las Vegas…

• less than a min read
5G , meltdown , ken thompson , JUG , CES2018 , Spectre , 5nm , what's for breakfast? , JasperGold

Verification

User Extensions to DUT Error

A question was raised to stackoverflow about how can one extend the dut _error()…

• 2 min read
Specman , e code , advanced verification , e language

Verification

App Note Spotlight - Introduction to Connect Modules

Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an…

• 3 min read
app note , Functional Verification , App Note Spotlight , Connect Module , mixed signal

Breakfast Bytes

Post-Silicon Compute

At the SEMI Strategic Materials Conference (SMC) a few weeks ago, Lucian Shifren…

• 6 min read
moore's law , ARM , power , DTCO

The India Circuit

Exciting Trends in 2018: An Interview with Jaswinder Ahuja

Jaswinder Ahuja is well-known to everyone in the semiconductor and electronics industry…

• 5 min read
mahindra & mahindra , Electronic System Design and Manufacturing , startups , Tata Motors , Maruti , electric vehicle , 2018 , ESDM

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar continues his explanation of…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

Virtuoso System Design Platform Is Product of the Year

The title of this post says it all, but I'd better add a bit of color. Cadence was…

• 5 min read
virtuoso system design platform , Virtuoso , Allegro

Breakfast Bytes

2017: A Year in Breakfasts

So 2017 is over. Taylor Swift got into trouble for saying it was a great year and…

• 6 min read
security , Automotive , risc-v , nanosheet , broadcom , Qualcomm , 5nm , nanowire

Verification

Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review

It’s always good to hear what real users think of products. Here is a very detailed…

• 3 min read

Verification

Register for the UVM Register Layer Webinar on January 12!

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim…

• less than a min read
webinar , Doulos , xcelium , uvm register layer

Breakfast Bytes

GLOBALFOUNDRIES 7nm

Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES…

• 3 min read
GlobalFoundries , 7nm , EUV , IEDM

Analog/Custom Design

Automatically Reusing an SoC Testbench in AMS IP Verification

The complexity and size of mixed-signal designs in wireless, power management, automotive…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal solution , analog , Mixed-Signal , analog/mixed-signal , Virtuoso environment , mixed-signal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)

Enabling Constraint-Driven Design With the pre-layout testbench built, populated…

• 5 min read
Serial link analysis , SI , Constraint Driven Design , Multi-Gigabit , PCIe , Signal Integrity , Sigrity

Breakfast Bytes

CES18 Preview

It's the start of a new year and that means it is the Consumer Electronics Show in…

• 9 min read
ces 2017 , deep learning , CES , audio , inception , atmos , Dolby , Tensilica , vision , neural networks

Breakfast Bytes

What is Meltdown? How Can It Affect Both Intel and Arm?

If you pay attention to anything to do with processors, security, or even investment…

• 8 min read
security , Intel , meltdown , x86 , ARM

Breakfast Bytes

What's For Breakfast? Video Preview January 8th to 12th 2018

https://youtu.be/txCnT3N4OSY Coming from Executive Briefing Center (camera Sean…

• less than a min read
Consumer Electronics Show , CES , CES2018 , semi , Virtuoso , ARM
CDNS - Fix Layout Hompage