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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

What Is Automotive Tool Confidence Level 1?

ISO 26262 is the functional safety standard for automotive, as you probably already…

• 4 min read
tcl1 , tool confidence level , ISO 26262 , Breakfast Bytes , tcl

Breakfast Bytes

What's For Breakfast? Video Preview November 14th to 18th

https://youtu.be/OQ1c30nbD0s Monday: Red Hat's Jon Masters talks about ARM…

• less than a min read
Automotive , ARM Techcon , Jasper User Group , risc-v , NXP , jasper gold , JUG , formal , risc-v foundation , google , red hat , Jasper , open source , mobile , ISO 26262 , ARM , linux , Formal verification , verification

Breakfast Bytes

Moore and Medical at ARM TechCon

The second keynote on the first day of ARM TechCon was a double act with Greg Yeric…

• 7 min read
security , greg yeric , ARM Techcon , IoT , 28nm , 3nm , 5nm7nm , Mike Muller , medical , moore's law , privacy , ARM , Breakfast Bytes , 2nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Industry Trends and Requirements for Autonomous Driving

In this week's Whiteboard Wednesdays video, the first in a three part series focusing…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety , automotive electronics

Breakfast Bytes

Who Wrote the Book on Formal Verification?

Who wrote the book on formal verification? Depending on whether you want to take…

• 5 min read
Intel , Jasper User Group , JUG , formal , CDC , Jasper , property checking , Equivalence Checking , jug 2016 , clock domain crossing , ARM , Breakfast Bytes , Formal verification , verification

Analog/Custom Design

Virtuoso Video Diary: I Am Not Promoting Layout Hierarchy Manipulation!

Are you contemplating manipulating your layout hierarchy by adding or removing a…

• 5 min read
Flatten , Transparent instances , Virtuoso Video Diary , Connectivity-driven , Make Cell , XL-compliance , Layout hierarchy manipulation , Custom IC Design , Virtuoso Layout Suite XL

Breakfast Bytes

The Amazing Raspberry Pi Story

Eben Upton gave a spellbinding keynote at ARM TechCon on the history of Raspberry…

• 9 min read
BBC , Raspberry Pi , Cambridge , acorn , british broadcasting corporation , ARM , Breakfast Bytes

Breakfast Bytes

Automotive Security: A Hacker's Eye View

Charlie Miller gave a keynote at ARM TechCon on automotive security. He is regarded…

• 8 min read
security , Automotive , onstar , uber , jeep , chris valasek , charlie miller , tesla , wired magazine , Breakfast Bytes

Verification

Analog Devices Promotes Portable Stimulus at DVClub

If you’re not familiar with the series of DVClub events held in North American, Europe…

• 3 min read
Analog Devices. ADI , pswg , cadence , debug , System Design and Verification , Dave Brownell , software , Accellera , System Design & Verification , portable stimulus , System Design and Verification , verification

Breakfast Bytes

What's For Breakfast? Video Preview November 7th to 11th

https://youtu.be/n4jz8shM1hM Monday: The amazing story of Raspberry Pi as…

• less than a min read
security , Automotive , greg yeric , ARM Techcon , Jasper User Group , Low Power , trustzone , Raspberry Pi , jasper gold , palladium z1 , eben upton , JUG , IoT , tcl1 , Palladium , Jasper , Mike Muller , medical , Internet of Things , Power Analysis , ISO 26262 , ARM , Formal verification

System, PCB, & Package Design 

How to Address the Challenges of Serial Link Design and Analysis

What is a serial link? It's an interface where data is serialized for high-speed…

• 3 min read
Serial link analysis , PCB , SI , IBIS-AMI , Signal Integrity , Sigrity , High Speed design , Allegro

Breakfast Bytes

Automotive Is a Pot of Gold Guarded by a Dragon

One of the big themes of pretty much any conference on semiconductors these days…

• 6 min read
Automotive , functional safety , tool confidence level , DVcon , DVCon Europe , ISO 26262 , optima , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimized FFTs on the Tensilica ConnX BBE32EP DSP

Fast Fourier transform (FFT) is a key kernel in almost all DSP applications, and…

• less than a min read
DSP , Whiteboard Wednesdays , baseband , ConnX , radar , Tensilica , signal processing , FFT

Verification

Genie in a Mouse Click: Indago Protocol Debug App

Do you remember what life was like before the internet and smart phones? If you wanted…

• 4 min read
Productivity Tool , Verification IP , and Verification IP' , VIP , Indago Protocol Debug App , design , 'Tensilica

Breakfast Bytes

Wave Computing: a Dataflow Processor for Deep Learning

On the first day of the Linley Processor conference someone told me that he was really…

• 4 min read
deep learning , tpu , wave computing , DPU , tensor flow , dataflow computing , Breakfast Bytes , dataflow processor

Breakfast Bytes

Segars and Son

When I was growing up, there was a TV show in the UK called Steptoe and Son, and…

• 5 min read
ARM Techcon , Simon Segars , IoT , masayoshi son , Internet of Things , arm holdings , ARM , Breakfast Bytes

Academic Network

Students from Tsinghua University Visit Cadence Beijing

On October 20, 2016, 12 Masters and Ph.D. students mostly from Institute of Microelectronics…

• less than a min read
Cadence Academic Network

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Arc-aware routing with enhanced contour hug saves…

Enhanced Contour Routing is a new prototype feature in the Cadence® Allegro® PCB…

• 1 min read
Allegro 17.2 , Routing , Rigid-Flex , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

Automotive at Linley: Intelligent Vehicles and Intelligent Intersections

The whole afternoon the second day of the Linley Processor Conference was dedicated…

• 5 min read
Automotive , NXP , linley processor conference , tensilica vision , mike demler , Automotive Ethernet , Linley , autonomous vehicles , Breakfast Bytes
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