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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

The SDE Circle of Life

There seems to be a big picture phenomenon that I like to call the System Design…

• 5 min read
Automotive , SDE , mobile , system design enablement

Verification

A Seamless Path to the Portable Stimulus Standard

In our last blog post , we reviewed some of the activities at the recent Design and…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

Léman Micro Devices: Blood Pressure on Your Smartphone

One of the most interesting things I saw at MWC was a meeting I had with Mark-Eric…

• 6 min read
Léman Micro Devices , medical electronics , mobile , cadence hosted design environment , blood pressure , Smartphone

Breakfast Bytes

TSMC Technology Symposium 28...22...16...12...7...

This is the second of two posts about last week's TSMC Technology Symposium. The…

• 7 min read
OIP , n5 , 12FFC , TSMC , TSMC Technology Symposium , n7+ , n7

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to Convolutional Neural Networks (CNN)

In this week's Whiteboard Wednesdays video, the first in a two-part series, Megha…

• less than a min read
Automotive , deep learning , vision , convolutional neural networks , mobile , ADAS , CNN

Breakfast Bytes

What's For Breakfast? Video Preview March 27th to 31st 2017

https://youtu.be/-_33atq9vRY Coming from National Automobile Museum, Reno,…

• less than a min read
ESDA , circle of life , lanza techventures , Lucio Lanza , system design enablement , SDA , esd alliance , virtual dummy metal fill

Breakfast Bytes

TSMC Technology Roadmaps

TSMC had their annual Technology Symposium last week. As always, my post comes with…

• 6 min read
Automotive , n5 , IoT , TSMC , HPC , n7 , mobile , n10

Academic Network

The Worldwide MEMS Design Contest Officially Starts

Cadence, X-FAB, Coventor and Reutlingen University have Selected 10 Design Teams…

• 2 min read
Cadence Academic Network , X-FAB , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Mixed-Signal , Coventor

Breakfast Bytes

CDNLive Silicon Valley Preview

Yes, it's that time of year again. Just like a cat has nine lives, Cadence has nine…

• 2 min read
microsoft , CDNLive , Santa Clara Convention Center , CDNLive Silicon Valley

Breakfast Bytes

Dracula, Vampire, Assura, PVS: A Brief History

Cadence was created from the merger of SDA and ECAD, as you probably know. SDA had…

• 9 min read
Extraction , Dracula , DRC , vampire , design rule check , Assura

Breakfast Bytes

Andy Bechtolsheim Keynote on the Future of Networking

At the recent Linley Cloud Hardware Conference, the keynote was given by Andy Bechtolsheim…

• 7 min read
andy bechtolsheim , arista networks , andreas bechtolsheim , linley cloud hardware conference , Linley

Breakfast Bytes

TSMC Announces New 12FFC Process

Today at the TSMC Technology Symposium, Cliff Hou, TSMC's VP of R&D, is set to announce…

• 4 min read
Design IP , 12FFC , TSMC , TSMC Technology Symposium , 12nm , InFO , 7nm

Breakfast Bytes

What's For Breakfast? Video Preview March 20th to 24th 2017

https://youtu.be/Qm8epP4YobA Coming from TSMC Technology Symposium, Santa Clara…

• less than a min read
Léman Micro Devices , CDNLive , SDE , 12FFC , TSMC , TSMC Technology Symposium , InFO , mobile , blood pressure , system design enablement , 7nm , Smartphone

Analog/Custom Design

Virtuoso Video Diary: Real-Time Tuning—A Lot More Than Just an Assistant!

Have you ever found yourself in situations where you’re not sure which values of…

• 3 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Whiteboard Wednesdays

Whiteboard Wednesdays - Display Stream Compression: Higher Display Resolutions in…

In this week's Whiteboard Wednesdays video, Alex Passi takes a closer look at Display…

• less than a min read
mobile devices , Whiteboard Wednesdays , MIPI , MIPI protocols

Breakfast Bytes

Cadence at MWC: Does This Headset Make Me Look Silly?

Cadence has attended MWC ever since it acquired Tensilica, and they attended for…

• 4 min read

Digital Design

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

• 3 min read
Physical verification , DRC , design rule check

Breakfast Bytes

ESD Alliance Panel on Energy Policy for the IoT Era

BREAKING NEWS: I just received an email that the panel I wrote about here has been…

• 4 min read
california energy commission , energy policy , ESDA , IoT , Internet of Things , san jose city hall , cec , esd alliance

Verification

Static Members in e

How do you define elegant or clean code? Usually, you know it when you see it; defining…

• 9 min read
Specman , Incisive , e language , static , xcelium , verification
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