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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

The Evolution of MIPI DSI

The MIPI DSI specification has come a long way from the days of its early introduction…

• 2 min read
Verification IP , MIPI Alliance , IoT , VIP , MIPI , DSI , Tensilica , design , Internet of Things , and Verification IP

Breakfast Bytes

CDNLive Bengaluru: Day 2

CDNLive Bengaluru takes place over two days. But it is organized very differently…

• 7 min read
NXP , CDNLive India , CDNLive , whats for breakfast , cdnlive bengaluru , implementation , tapeout

Breakfast Bytes

CDNLive Bengaluru: Day 1

As I did at the Design Automation Conference in Austin earlier this year, I will…

• 7 min read
CDNLive , bengaluru , bangalore , Breakfast Bytes , analog devices

Whiteboard Wednesdays

Whiteboard Wednesdays—Radar Signal Processing for Automotive Applications

In this week's Whiteboard Wednesdays video, the first of a two-part series, Pushkar…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , radar , Tensilica

Breakfast Bytes

CDNLive Bengaluru, a Long Journey

I've not been to Bengaluru for about 20 years, when I ran engineering at Compass…

• 3 min read
CDNLive India , bengaluru , Cadence India , Breakfast Bytes

System, PCB, & Package Design 

Five Industry Experts Coming to CDNLive Boston to Discuss Signal and Power Integrity…

Who Are They? Istvan Novak – Senior Principal Engineer at Oracle Kevin Roselle…

• less than a min read
CDNLive , Signal Intregrity , Power Integrity , Boston , PCB design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Persistent Snap and Select? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces a few new features that provide…

• 2 min read
PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

Breakfast Bytes

What's for Breakfast? August 8th

This is the first weekly video "What's for Breakfast?" that previews the blog entries…

• 1 min read
risc-v , CDNLive India , CDNLive , preview , whats for breakfast? , cdnlive bengaluru , mobilemobile 5g , Breakfast Bytes

Breakfast Bytes

Breakfast Bytes Guide to Japan Travel

Cadence was shut down for the week of July 4th, so I went to Japan with a friend…

• 5 min read
tsukiji , kyoto , osaka , tourism , narita , kansai , japan , travel , haneda

Breakfast Bytes

Merger Mania

At the recent GSA Silicon Summit at the Computer History Museum in Mountain View…

• 6 min read
Wally Rhines , merger mania , gsa silicon summit , mergers , gsa , Breakfast Bytes , acquisitions , Mentor

Breakfast Bytes

Chipworks Looks at Smartphones

Chipworks buys hundreds of devices every year and strips them down to look at the…

• 4 min read
Intel , Apple , Samsung , TSMC , Linley , wearables , mobile , GlobalFoundries , smartphones , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Using Processor Clusters to Implement Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen describes how to use processor…

• less than a min read
Whiteboard Wednesdays , IP , processor clusters , Tensilica , neural networks , CNN

SoC and IP

Fastest Octal SPI Flash Interface Available Now From Cadence

Flash memory is being utilized in computers and electronic devices found in Automotive…

• 1 min read
PHY , octal spi , spi , nor flash

SoC and IP

Cadence at Flash Memory Summit 2016: Octal SPI, eMMC 5.1, ONFi 4, and Tensilica SSD…

If you design with flash memory components or IP solutions, head on over to the Santa…

• 1 min read
Verification IP , Design IP , Memory , VIP , Tensilica , semiconductor IP , Design and Verification IP , Design IP and Verification IP , memories

Breakfast Bytes

Smartphones: Linley's Annual Review

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables…

• 3 min read
Apple , Samsung , wearables , mobile , Smartphone , Huawei

Analog/Custom Design

Virtuoso Variation Option: Reliable High-Yield Design with Scaled-Sigma Sampling

What’s Scaled-Sigma Sampling? Scaled-sigma sampling (SSS) is an efficient algorithm…

• 4 min read
Variability Aware Design , scaled sigma sampling , ADE , IEEE , Variation , yield

Analog/Custom Design

Analog Design Resonance: Quick and Efficient Regression Scripts–Now Possible with…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity…

• 3 min read
ADE Explorer , ADE , Custom IC Design , ADE Assembler

Breakfast Bytes

CDNLive Boston Preview

The full agenda for CDNLive Boston is now available. This is really "East Coast"…

• 2 min read
CDNLive , Power Integrity , cdnlive boston , Boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

Nokia's Rise and Fall...and Maybe Rise Again

If you live in the US, then it is hard to believe how dominant Nokia was in mobile…

• 7 min read
microsoft , nokia , elop , mobile , Breakfast Bytes , iPhone
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