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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Model Management? 16.6 Has a Few New Enhancements!

New Model Management capabilities are now available in the SPB 16.6 Allegro Design…

• less than a min read
Allegro 16.6 , flow manager , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , setup , design data management , design , PCB design , Grzenia , model editor , library , ADW , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Smart Layer Behavior for Add Connect? It’s in…

When using the Add Connect command in the 16.6 Allegro PCB Editor , the active layer…

• less than a min read
PCB , Allegro 16.6 , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Two-Layer PCB Support? Check Out 16.6!

By default, the top and bottom stackup layers do not support the placement of embedded…

• 2 min read
Allegro 16.6 , layer stacks , via , PCB design , Grzenia , Allegro PCB Editor , Allegro

Analog/Custom Design

Adding Weighted Noise Via Calculator Custom Function

Applying a weighting factor to a Noise Summary run requires lots of steps and the…

• 1 min read
Analog Design Environment , ADE XL , ADE , ViVA , Custom IC Design

Analog/Custom Design

Virtuoso Video Diary: Getting Started with the New Virtuoso ADE Product Suite

Hey, did you hear the buzz around the new Virtuoso ADE product suite , which was…

• 3 min read
Analog Design Environment , Virtuoso ADE Verifier , ADE GXL , Analog Simulation , ADE XL , ADE , Block-level simulation , Monte Carlo , Virtuoso , ADE-GXL , ADE-XL , Virtuoso Video Diary , Custom IC Design , Virtuoso ADE Explorer , Virtuoso ADE Assembler

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support (Reason…

Why Rigid-Flex? For nearly all applications, customers continue to demand smaller…

• 4 min read
Allegro 17.2 , Rigid-Flex , MCAD-ECAD , PCB design , Allegro PCB Editor , IPC-2581 , Why Move Up to 17.2

Breakfast Bytes

IEDM, New This Year

It might seem a bit premature to be talking about IEDM since it isn't until December…

• 3 min read
International Electron Devices Meeting , 5nm test chip , IEDM

Breakfast Bytes

Gimme a G...Gimme a 3...Whatcha Got?...DSP

Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing…

• 2 min read
linley mobile and wearables , linley group , Fusion G3 , Linley , Tensilica , linley mobile , Tensilica Fusion G3 DSP , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support—Empowering Learning! New Learnings—Sigrity 2016

Cadence Online Support Features Setting up ‘My Alerts” The My Alerts section displays…

• 1 min read
PCB SI , Constraint-driven PCB Design flow , PDN , Signal Intregrity , SigXP UI , PCB Signal and power integrity , Power Integrity , "PCB SI" , Signal Integrity , "PCB design" , PCB Signal integrity , Allegro PCB SI , SI analysis and modeling , power

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to the New Tensilica Fusion G3 DSP

In this week's Whiteboard Wednesdays video, Paul Garden provides an introduction…

• less than a min read
DSP , Whiteboard Wednesdays , IP , floating point DSP , Tensilica , Tensilica IP

Breakfast Bytes

Pathfinding Beyond 5nm

One of the most interesting sessions that I attended at SEMICON West the week before…

• 4 min read
tunnel fet , IBM , carbon nanotube , semicon west , imec , coolcube , 5nm , FD-SOI , silicon nanowire

Breakfast Bytes

CDNLive India

CDNLive India is coming up on August 9th and 10th in Bengaluru. I will be there and…

• 2 min read
CDNLive India , CDNLive , bengaluru , bangalore

System, PCB, & Package Design 

Cadence Online Support—Empowering Learning! New Learnings from June 2016

Cadence Online Support Features " You might also be interested in ” Section …

• 2 min read
16.6 , PCB Signal and power integrity , "PCB design" , application note , Allegro

System, PCB, & Package Design 

Cadence Online Support – Empowering Learning! New Learnings - February, March 20…

Cadence Online Support Features “ Most Popular ”: This section displays content…

• 3 min read
PCB , Allegro Design Entry , DEHDL , Capture CIS , Cadence Online Support , Allegro Design Workbench , "PCB design" , Allegro PCB Editor , ConceptHDL , application note , ADW , Allegro

System, PCB, & Package Design 

What’s Good About PSpice.com? You’ve Got to See This New Resource Site!

PSpice.com is a new user-community web portal that lets designers, partners, and…

• 1 min read
cadence , AMS simulator , PSPICE , Grzenia

Breakfast Bytes

System-Level Functional Verification and Power Analysis

With DAC and other events during May and June, I am only now wrapping up stuff I…

• 2 min read
Functional Verification , Power Analysis , system level functional verification , system level power analysis

System, PCB, & Package Design 

10 Top Reasons to Move Up to Allegro 17.2-2016 Release

The Allegro 17.2-2016 release , the largest in the past 10 years, became available…

• 8 min read
Constraint-driven PCB Design flow , Allegro 17.2 , Allegro GUI , Routing , Constraint Manager , Rigid-Flex , OrCAD , Sigrity , Allegro PCB Editor , Why Move Up to 17.2 , Allegro

Breakfast Bytes

200mm Fabs Awaken

Modern fabs use 300mm (12") wafers. Older fabs have used 200mm (8") wafers since…

• 5 min read
semicon west , semi , fab outlook , 200mm , semi/gartner symposum

SoC and IP

Needs of Energy-Efficient Networking While Using 10 Gigabit Ethernet

Growing deployment level of 10 Gigabit Ethernet in datacenters and automotive infotainment…

• 1 min read
10G-KR , Ethernet
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