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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

Breakfast Bytes

Andrzej Strojwas Receives the 2016 Kaufman Award

Last night was the annual Kaufman Award dinner to present the award to this year…

• 6 min read
Kaufman Award , kaufman award dinner , andrzej strojwas , pdf solutions

Breakfast Bytes

What's For Breakfast? Video Preview January 30th to February 3rd 2017

https://youtu.be/NxgrCMJYRew Coming from Kaufman Award Dinner Monday: The…

• less than a min read
asml standard node , formal , Kaufman Award , STA , andrzej strojwas , variability , standard node , Formal verification

Breakfast Bytes

SPIE Advanced Lithography Conference

SPIE is the international society for optics and photonics, with the purpose of …

• 4 min read
lithography , imec.spie advanced lithography , SPIE

Breakfast Bytes

Frank Chen of a16z on 16 Things About Autonomous Vehicles

In a recent a16z presentation, Frank Chen, a partner at Andreessen-Horowitz, says…

• 6 min read
autonomous cars , self-driving cars , a16z , autonomous vehicles

Breakfast Bytes

ENNS 2017: Deep Learning, the New Moore's Law

One of the hottest areas in systems right now is deep learning: neural networks,…

• 3 min read
CVPR , deep learning , enns 2017 , CNN

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: The Early Days

In this week's Whiteboard Wednesdays video, the second in a three-part series, Scott…

• less than a min read
Verification IP , Whiteboard Wednesdays , Scott Jacobson , VIP , Ethernet

Analog/Custom Design

New Virtuoso ADE Suite Wins Product of the Year

Cadence today announced that its next-generation Virtuoso® Analog Design Environment…

• 1 min read
ade suite , electronic products , product of the year

Breakfast Bytes

Nibbles: Breakfast Bytes Predictions 2017

It's that time of year when pundits try and predict major changes that will happen…

• 3 min read
2016 predictions , 2017 predictions

Verification

Bare Metal Tests and Hardware-Software Co-Verification

One interesting question that arises from time to time is whether the Cadence® Perspec…

• 4 min read
hardware-software co-verification , uvm , pswg , Acceleration , Perspec , virtual platform , System Design and Verification , Emulation , System simulation and analysis , Accellera , FPGA prototypes , testbench , portable stimulus , silicon , bare metal , verification

Breakfast Bytes

RISC-V "The thing that you learn and the thing that you use are the same"

The Electronic System Design Alliance (fka EDAC) has been organizing evening meetings…

• 7 min read
risc-v , cadence , isa , Jim Hogan , instruction set architecture , sifive , esd alliance

Analog/Custom Design

Virtuoso Video Diary: Demystifying the Abstract

You heard it right! It’s Virtuoso Abstract Generator, the popular library modeling…

• 3 min read
AG , abstract , Virtuoso Video Diary , Custom IC Design , Virtuoso Layout Suite XL

Breakfast Bytes

Automotive at CES

Automotive was huge at CES. A lot of it went for the glamour without really having…

• 3 min read
Automotive , NVIDIA , Qualcomm

Whiteboard Wednesdays

Whiteboard Wednesdays - Interconnect Design Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss takes a closer look at the…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , MIPI , MIPI protocols , Nimrod Reiss , verification

Breakfast Bytes

Security in 2016 and 2017

It's the start of the year, plus the Consumer Electronics Show is over. I've already…

• 3 min read
security , botnets , mirai , drones , Singapore

Analog/Custom Design

Virtuoso Video Diary: Using the Hierarchical Color Locking Check

As you incrementally build your design and decompose the layout geometry into masks…

• 2 min read
dbLock , Hierarchical Color Locking Conflicts , Multiple Patterning Technology , HCL , Coloring Engine , Virtuoso Video Diary , Hierarchical Color Locking Check , multi-patterning technology , Custom IC Design , MPT

Academic Network

Cadence Academic Network Events in Russia

Despite all of the recent political tensions, Russia remains an attractive market…

• 2 min read
MIET , Cadence Academic Network , MEPHI , RusNano , Russia

Breakfast Bytes

5G is Coming. Qualcomm Keynote at CES

Steve Mollenkopf, the CEO of Qualcomm, gave one of the keynotes at the Consumer Electronics…

• 4 min read
5G , Automotive , Consumer Electronics Show , CES , IoT , Qualcomm , mobile

Breakfast Bytes

Bluetooth 5, 4.2, Bluetooth Classic, and Bluetooth LE...Confused Yet?

What is Bluetooth 5? 4.2? Bluetooth Classic? Bluetooth Smart? Low Energy? The naming…

• 6 min read
BLE , bluetooth , bluetooth 4.2 , Bluetooth 5.0 , Breakfast Bytes

Breakfast Bytes

Security the Google Way

The latest RISC-V workshop was held at Google. In the middle of the day, there was…

• 3 min read
security , risc-v , nsa , google , bios lockdown , rowhammer , Breakfast Bytes
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