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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

System Design Enablement with Cadence and TSMC

System-on-chip (SoC) designers are always optimizing what has become known as PPA…

• 3 min read
Low Power , bvp.system-ppa , virtual platform , TSMC , Tensilica , power , Breakfast Bytes

Verification

Back in the Saddle Again

Nearly five years ago, I signed off with my last blog post in the Cadence Community…

• 3 min read
pswg , Perspec , System Design and Verification , System simulation and analysis , Accellera , portable stimulus , System Design and Verification , verification

Breakfast Bytes

Mellanox: Using Palladium ICA Mode

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium…

• 3 min read
Yaron Netanel , CDNLive , debug , mellanox , Palladium , in-circuit acceleration , ICA , cdnlive israel , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 26th to 30th (video)

https://youtu.be/1le_bd4o01Q Monday: System Design Enablement with Cadence and…

• less than a min read
OIP , Memory , MemCon , LPDDR , liinley , SDE , TSMC , antiportfolio , DDR , system design enablement , bessemer ventures , power , microprocessor

Breakfast Bytes

How to Connect Sensors with I3C

A couple of sessions at MIPI DevCon last week were on I3C. This is a new generation…

• 6 min read
MIPI , i2c , sensors , mobile , I3C

Analog/Custom Design

Virtuoso Video Diary: SKILL IDE Performance Analysis Tools

As a SKILL code developer, do you spend a major chunk of your time in fine-tuning…

• 2 min read
Team SKILL , programming , Virtuoso Video Diary , software development , SKILL IDE , Custom IC Design , SKILL++ , Virtuoso Layout Suite , SKILL

Breakfast Bytes

שלום from CDNLive Israel

Shalom. Today is CDNLive Israel in Tel Aviv. At least getting here from San Francisco…

• 5 min read
CDNLive , Lip-Bu Tan , cdnlive israel , perlmutter

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the PCIe Standard

In this week's Whiteboard Wednesdays video, Lana Chan explores the history of PCI…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express

Breakfast Bytes

MIPI: Not Just Mobile Any More

On September 14 and 15, MIPI held its first developer conference. For more background…

• 3 min read
5G , Automotive , 4G , CSI-2 , Standards , MIPI , mipi devcon , ADAS , I3C , Breakfast Bytes

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Padstack Editor – More Than Just a New GUI…

Customer inputs are key to product improvements I can read your minds as you…

• 5 min read
backdrill , Allegro 17.2 , keepouts , masks , padstack , PCB design , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Signal and Power Integrity Masterclass

At CDNLive Boston, I moderated a panel session on signal and power integrity with…

• 9 min read
DDR4 , CDNLive , dc-dc converters , IBM , Cisco , Oracle , cdnlive boston , advanced bus analysis , Qualcomm , compliance methodology

Academic Network

Cadence at the VLSI Design/CAD 2016 Symposium

Great Academic Networking in Taiwan With the support of the Cadence Academic Network…

• less than a min read
VLSI , Cadence Academic Network

Academic Network

ESSCIRC and ESSDERC in Lausanne

Since the year 2000, the European Solid-State Device Research Conference (ESSDERC…

• 2 min read
Cadence Academic Network , esscirc , essderc

Computational Fluid Dynamics

Masten Space Systems: Reuseable Space Craft Innovation With Cadence CFD Software

Until very recently, rockets that launched satellites into orbit were completely…

• 5 min read

Breakfast Bytes

Are These Codecs Any Good? Netflix Tests Them

A codec compresses data for transmission. The first codec I had any close encounter…

• 5 min read
GSM , audio codec , H.265 , codec , netflix , mobile , h.264 , video codec , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 19th to 23rd (video)

https://youtu.be/KKiIDaN-3CE Monday: At CDNLive Boston I moderated a panel session…

• less than a min read
cdnlive tel aviv , Paul McLellan , CDNLive , debug , mellanox , VIP , MIPI , Power Integrity , i2c , cdnlive boston , mipi devcon , Indago , Signal Integrity , cdnlive israel , I3C , what's for breakfast? , protocol verification , Breakfast Bytes , verification

Breakfast Bytes

Emulation Productivity: Beyond the Specs

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information…

• 5 min read
CDNLive , palladium z1 , Protium , Palladium , cdnlive boston , Emulation , FPGA prototyping , Breakfast Bytes

Academic Network

Increasing Functional Verification Coding Process Efficiency

In EDA you traditionally have to know several modelling languages for several domains…

• 3 min read
eclipse , Cadence Academic Network , Functional Verification , DVT , Coding Efficiency

Breakfast Bytes

Everything That's New About Ethernet

IEEE 802.3 is the standard number for various flavors of Ethernet. With Ethernet…

• 6 min read
Ethernet standards , Ethernet , 802.3 , IEEE , Breakfast Bytes
CDNS - Fix Layout Hompage