Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

• less than a min read
Whiteboard Wednesdays , machine learning , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 2nd to 6th 2017

https://youtu.be/uT2vXsXHV6s Coming from my car (camera Sean) Monday: AMD…

• less than a min read
deep learning , tensiilica , formal , EDPS , sjsu , portabe stimulus standard , Jim Hogan , pss , Formal verification

Verification

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

• 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation

Breakfast Bytes

SEMI Strategic Materials Conference

Yesterday I wrote about EDPS, which takes place at SEMI. Today, I'm writing about…

• 6 min read
China , semiconductor equipment , AMD , semi , moore's law , ARM , Breakfast Bytes

Learning and Support

Follow Video-Embedded Troubleshooting Articles for Easier Debugging

Finding a way out of situations is routine in today’s ever changing world—more so…

• 1 min read
COS , Self-Help , videos , Self Learning , what's new , Cadence Online Support , Support , troubleshooting , Cadence Support Portal , Cadence support

Breakfast Bytes

Solving the Design to Manufacturing Problems in Milpitas

HOT NEWS: In case you missed it, right at the end of last week, British GPU and CPU…

• 8 min read
Cisco , hvm , manufacturing , synopsys , data-centric computer architecture

Academic Network

EDA Summer Camp—Cadence Taiwan Hosts Top University Students

To help more students majoring in Electronics Engineering increase their understanding…

• 1 min read
Cadence Academic Network , academic workshop , academia , EDA

Verification

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

• 1 min read
Interconnect Workbench , customer feedback , success story , Palladium , Renesas

Analog/Custom Design

The Art of Analog Design: Part 3, Monte Carlo Sampling

In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider…

• 4 min read
Analog Design Environment , APS , ADE Explorer , Analog Simulation , analog , ADE , Monte Carlo , Analog Design Environment , ViVA , ADE Assembler , Cusstom IC Design

Breakfast Bytes

What's For Breakfast? Video Preview September 25th to 29th 2017

https://youtu.be/Uubpn09k83U Coming from Testarossa Winery, Los Gatos (camera…

• less than a min read
semi , business models , EDPS , sjsu , Jim Hogan , neural nets , smc

Analog/Custom Design

Virtuosity: Sweeping Multiple DSPF Views in ADE

Wouldn't it be great if you could have a view for your DSPF files and sweep them…

• 3 min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , DSPF , ADE , Block-level simulation , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , ViVA , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

Show Me the Money

I have put out some posts about generic business models and startups. However, if…

• 7 min read
investors , EDA , startups , Breakfast Bytes

Breakfast Bytes

Coincidence and Another Record

Record 1 I recently reached a sort of record that I detailed in my post The 500th…

• 6 min read
SIA , hock tan , gsa , Breakfast Bytes

The India Circuit

CDNLive India 2017: ThinCi on AI, Machine Learning and Deep Learning

Last week’s blog was about Venu Puvvada’s keynote at CDNLive India. Today’s blog…

• 4 min read
artificial intelligence , CDNLive India , deep learning , CDNLive , ThinCi , machine learning

Breakfast Bytes

India, Singapore, Hong Kong

What do India, Singapore, and Hong Kong have in common? Well, I visited them all…

• 8 min read
CDNLive , lee kuan yew , hong kong , sir john cowperthwaite , bangalore , Breakfast Bytes , India , Singapore

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementation Challenges of Embedded Automatic Speech Recognition…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

• less than a min read
Whiteboard Wednesdays , Automatic Speech Recognition

SoC and IP

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

• 1 min read
USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Breakfast Bytes

CDNLive India 2017 Trip Report

I went to Bangalore to CDNLive India. It has a different structure from the other…

• 6 min read
ml , CDNLive India , dl , CDNLive , machinelearningdeeplearning , AI , Breakfast Bytes

Analog/Custom Design

Virtuosity: Sweeping Multiple Config Views

Before IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in…

• 2 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler
CDNS - Fix Layout Hompage