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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Verification

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time…

• 2 min read
virtual platforms , virtual prototypes , System Design and Verification , OSCI , DVcon , Accellera , Jim Hogan , IEEE P1666 , SystemC , NASCUG , SystemC Day

Digital Design

Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Si…

Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a…

• 2 min read
dynamic rail analysis , Static timing analysis , ets , EDI system , Signoff Analysis , DRC , design rules , LVS , SI analysis , EPS , noise analysis , EDI 10.1 , Virtuoso , Digital Implementation , In-Design Signoff , Timing analysis , Power Analysis , signoff , tapeout , IR drop , Digital end-to-end flow , EM Failures , timing convergence , DFM

Analog/Custom Design

Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM…

Circuits implemented using sub-micron technologies require designers to meet tighter…

• 9 min read
APS , characterization , Compact Modeling Council , model qualification , IBM , MMSIM , Monte Carlo , spectreMDL , Spectre , CMC , SOI , Custom IC Design , Spice model verification , BSIMSOI

System, PCB, & Package Design 

What's Good About PCB SI Signal Quality Screening? SPB16.3 has a Few New Enhancements

Signals are subject to degradation when they are transmitted through a channel. High…

• 3 min read
PCB SI , PCB , SI , SPB16.3 , Signal Intregrity , SigXP UI , Allegro 16.3 , SPB 16.3 , High Speed , SPB , PCB design , signal quality screening , SI analysis and modeling , Allegro

Verification

Celebrating the UVM 1.0 Release, or the Gadfly Eats a Little Crow

As I hope you have all seen by now, Accellera has announced the official production…

• 2 min read
uvm , methodology , Functional Verification , VIP , VIP-TSC , Register Package , Accellera , gadfly , verification

Verification

The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my…

• 4 min read
debug , C , system design , SystemC , Virtual Platforms , Synthesis , Modeling , C++ , debugging , simulation , System Design and Verification

Verification

Formal Driven MDV – A New Tool for your Toolbox

Have you considered adding formal to your metric driven verification flow? Maybe…

• 2 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , MDV , simulation , Formal verification

Verification

Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example…

• 2 min read
uvm , Functional Verification , EDA360 , Incisive , Accellera VIP TSC , synopsys , IES , Mentor

Verification

The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various…

• 4 min read
conformal , corner cases , clock domain crossings , CDC , bug , FIFO

Digital Design

Evolution of Design Exploration and Planning

The great architect Frank Lloyd Wright once said "you can fix it on the drafting…

• 2 min read
EDI , First Encounter , EDI system , partitioning , Floorplanning , encounter digital implementation system , Encounter Digital Implementation , Digital end-to-end flow , Floorplanning and Prototyping

Digital Design

Guest User Blog: dbShape For All Your Logical Operation Needs

This is a guest post from Jason Gentry at Avago. I hope you enjoy this useful piece…

• 4 min read
EDI , Avago , encounter , EDI 10.1 , dbShape , db access , Digital Implementation , Gentry , logical operations , tcl

System, PCB, & Package Design 

What's Good About Allegro Router and Highlighting? You’ll need the SPB16.3 Release…

Just a quick post this week on a new Allegro PCB Router feature in the SPB16.3 release…

• less than a min read
PCB , SPB16.3 , blind vias , Routing , specctra , Allegro 16.3 , layer stacks , SPB 16.3 , PCB Editor , Layout , via , design , "PCB design" , PCB design , highlighting , Allegro PCB Editor , buried vias , Allegro

Verification

The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this…

• 5 min read
ABV , methodology , verification strategy , coverage , metric driven verification (MDV) , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , metric-driven verification , coverage driven verification (CDV) , assertions , IEV , simulation , IFV

Verification

Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start…

• 3 min read
emulator , ASIC , Acceleration , virtual platform , System Design and Verification , OVM , Palladium , Low power verification and analysis , Emulation , virtual prototype , System Design & Verification , Hardware/software co-verification , simulation , verification

System, PCB, & Package Design 

Shorter, Predictable Design Cycles (SPDC) – Ensuring Critical Signals Have a Return…

This is third in the series of blog posts about making your design cycles predictable…

• 2 min read
PCB , DDR2 , High Speed , webinar , PCB design , return path , PCI Express , SATA , Standards based Interfaces , DDR3 , Allegro

Analog/Custom Design

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)

The design and verification methodology for analog circuits has not changed much…

• 3 min read
ABV , assertion-based , Analog Simulation , analog , SoC , Mixed-Signal , SVA , PSL , AMS simulation , assertions , mixed signal , wreal , Custom IC Design , verification

System, PCB, & Package Design 

What's Good About Allegro Measure, Grids and Formulas? See For Yourself in SPB16

This week, I’m tossing together a mix of a few new SPB16.3 Allegro PCB Editor features…

• 2 min read
grids , PCB , PCB Layout and routing , Allegro 16.3 , SPB 16.3 , SPB , formulas , PCB Editor , High-Density Interconnect , Layout , via , design , PCB design , Allegro PCB Editor , Cline change , HDI , microvia , Allegro

Analog/Custom Design

Advanced Mixed-Signal Designs Demand a Unified Methodology

Mobile, automotive, consumer and medical applications require the productive realization…

• 4 min read
conformal , RF , mixed-signal seminars , Low Power , CPF , abstraction , analog , ECOs , Mixed-Signal , Convergence , intent , Silicon Realization , mixed signal , signoff , SoCs

Verification

De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you…

• 2 min read
High-Level Synthesis , Registers , TLM , Models , C to Silicon , transaction level modeling , SystemC , Modeling , System Design and Verification
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