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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Sunday Brunch Video for 18th November 2018

https://youtu.be/G12sQpq0JSI Made on Maui (camera Carey Guo) Monday: Portable Stimulus…

• less than a min read
PCB , security , artificial intelligence , processor , Perspec , linley group , semi , Sigrity , pss , AI , Allegro

PCB、IC封装：设计与仿真分析

如何一劳永逸轻松对接三维建模专家

回想一下那个坐在角落里被一群博士们簇拥着的同事；人人都想找这位3D专家给自己的设计做3D结构分析。他/她好像无所不能，会使用一般人难以掌握的软件工具。 但是问题是…

• less than a min read
系统串行链路 , SI , Chinese blog , 3D EM , 3D EM HSSO , 3D EM高速结构优化器 , 中文 , 3D , HSSO , Sigrity , 高速结构优化 , 信号完整性 , Allegro

Breakfast Bytes

The Linley Halloween Processor Conference

Halloween saw the latest Linley Fall Processor Conference. It is only a few years…

• 10 min read
linley processor conference , wave computing , Linley , Tensilica , ARM

定制IC芯片设计

Virtuoso: 新序曲-新视角下的拥塞分析

总结: 敬请关注这种独特的布线功能集以及ICADVM 18.1中即将推出的Design Planner工具，并以全新的视角来体验新的拥塞分析辅助工具。

• less than a min read
Congestion Analysis , Chinese blog , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Space-based Router , Routing , Virtuoso Advanced Release , Congestion Assistant , Congestion Analysis Assistant , New in EDA , Custom IC Design , Virtuoso New Design , Design Planner , Custom IC

Analog/Custom Design

Virtuoso: The Next Overture – Concurrent Layout – a New Methodology for Team Des…

Any task when divided among multiple people gets done quickly... right? What if we…

• 4 min read
Chip finishing , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Layout , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

Breakfast Bytes

Mechanical, Thermal, EMI, SI, PI: PCB Design Needs Them All

Back in the days when Roger Moore was James Bond, there were various criticisms of…

• 3 min read
PCB , Signal Integrity , PCB design , Sigrity , thermal , Allegro

Breakfast Bytes

How to Find Primes

Primes are really important in encryption. In fact, the foundation of internet security…

• 9 min read
security , prime number , encryption , factorization

Whiteboard Wednesdays

Tensilica HiFi 5 DSP Enabling Machines for Voice UI

In this week’s Whiteboard Wednesday, Sachin Ghanekar, Design Engineering Group director…

• less than a min read
hifi 5 , Whiteboard Wednesdays , Tensilica , HiFi DSP

Breakfast Bytes

Bagels and Brains: SEMI's Artificial Intelligence Breakfast

A couple of weeks ago the Silicon Valley chapter of SEMI held a breakfast meeting…

• 7 min read
Intel , semi , machine learning , aws , Amazon , xilinx , ARM , AI

定制IC芯片设计

Virtuoso: 新序曲-Design Planner 工具简介

新版的Virtuoso平台（*ICADVM18.1）提供了突破性的分析功能和创新的仿真驱动版图设计，实现了更强大，更高效的设计，支持最先进的工艺技术。基于该解决方案…

• less than a min read
Chinese blog , Cadence blogs , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC , Layout Editing

Breakfast Bytes

Portable Stimulus and Correct Designs

The title of this post seems pretty generic, after all who wouldn't want correct…

• 4 min read
correct designs , Perspec , Accellera , pss

Breakfast Bytes

Sunday Brunch Video for 11th November 2018

https://youtu.be/deyk_MEkjZg Made at Cadence Diwali Celebration (camera Sean) Monday…

• less than a min read
Automotive , risc-v , China , Kaufman Award , IEDM

PCB、IC封装：设计与仿真分析

针对电气工程师的热管理基础——第一篇

作者：Lawrence Der 在过去，机械工程师全权负责产品的热力设计，包括产品的机械外壳和其它物理方面的设计；然而现在，热力设计问题却是要电气工程师来共同承担…

• less than a min read
热 , Chinese blog , 热分析 , 温度 , 中文 , PowerDC , 传热 , 热基础

Breakfast Bytes

Kaufman Award Dinner: The Tom Williams Story

Wednesday night it was the annual Kaufman Award Dinner to honor this year's recipient…

• 6 min read
kaufman dinner , scan , Scan test , IBM , Kaufman Award , tom williams , lssd , synopsys

Breakfast Bytes

RISC-V Summit Preview: Pascal or Linux?

Coming up in December, in the same week as IEDM, is the RISC-V Summit at the Santa…

• 3 min read
risc-v , Spectre , instruction set architecture

Breakfast Bytes

IEDM Preview: 3nm and More

A lot of aspects of EDA and semiconductor are fairly easy to predict: you read off…

• 5 min read
IBM , 3nm , Samsung , imec , gaa , tu dresden , IEEE , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays - How the Cadence 112G SerDes IP Solves the Challenges of Long…

In this week’s Whiteboard Wednesday, Wendy Wu explains what NRZ and PAM-4 signaling…

• less than a min read
Whiteboard Wednesdays , 100G Ethernet , 112G SerDes , PAM-4 , SerDes , 400G Ethernet , 800G Ethernet

Breakfast Bytes

Automotive Summit: Driving an Industry with Electronics

Coming up on November 14th is the Cadence Automotive Summit. This will be held on…

• 3 min read
Automotive , lidar , radar , Tensilica , vision , ISO 26262 , ADAS , ARM

The India Circuit

A Diwali with Green Crackers and Cooking Bots

It’s Diwali! My favorite festival out of all the many celebrations that we Indians…

• 3 min read
firecrackers , green cracker , air pollution , Diwali
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