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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Bulk Editing? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) release provides bulk editing support. This…

• 1 min read
PCB , Allegro Design Workbench , Library flow , Library and design data management , bulk editing , SPB , design data management , PCB design , SPB16.5 , Librarians , library , ADW , Schematic

Verification

Photo Essay and Comments on DAC 2012 in San Francisco, CA

In addition to the annotated image gallery (click here or on the image), below are…

• 3 min read
gallery , DAC , Joe Hupcey III , ABV , CDNLive , Functional Verification , formal , "Coverage Unreachability" , formal apps , Richard Goering , 20nm , Vigyan Singhal , bypass verification , Denali Party , UCIS , DVcon , Accellera , Lego , Hosted Design Solutions , DAC 2012 , robot , IEV , Oski , Rubik's Cube , Formal verification , IFV , cloud computing , verification

SoC and IP

Martin Lund on the Future of IP (Video Interview)

As SoC complexity continues to rise, more IP is being utilized, and the quality and…

• less than a min read
IP , Martin Lund , video , IP integration , Lund , Live Stream , future of IP , EE Times

Verification

Using Event Ports (With Edge Attribute) to Define Simulator Sensitive Events Rather…

There are two ways in e to define an event to be sensitive to a change of value in…

• 6 min read
AF , events , Specman , Synchronization , Functional Verification , event ports , ports , simple ports , e language , team specman , interface , edge attribute

System, PCB, & Package Design 

What's Good About Object Visibility Layers in DEHDL? The Secret's in the 16.5 Release

In the 16.5 Design Entry HDL (DEHDL) release, Object Visibility Layers are introduced…

• 1 min read
PCB , Allegro Design Entry , hierarchy , DEHDL , object visibility layers , hierarchical schematics , PCB Editor , Design Entry HDL , Front-end PCB design , design , PCB design , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

RF Engineering

Measuring Bipolar Transistor ft with Fixed Base-Collector Voltage

Recently I had a question from reader. He asked a good question: "How do you to measure…

• 2 min read
RF , RF Simulation , fixed base-collector voltage , parametric analysis , RFIC , bipolar transistor , measuring bipolar transistor ft , Schaldenbrand , analog , ADE , Vbc , Virtuoso , ViVA , RF design , transistor ft , testbench

System, PCB, & Package Design 

What's Good About PCB SI PDN Analysis? 16.5 Has Many New Enhancements!

As clock and data frequencies increase and high-speed systems become more densely…

• 4 min read
PCB SI , PCB , SI , PI , SiP , PCB PI , PDN , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , Power Integrity , High Speed , PCB power integrity , Allegro 16.5 , SPB , Power Delivery Network , full wave , Signal Integrity , full-wave , PDN Analysis , "PCB design" , field solver , PCB Signal integrity , Allegro PCB SI , PCB design , "PCB PI" , SPB16.5 , Allegro PCB Editor , SI analysis and modeling , "Power Delivery Network" , Predictable PCB design , Allegro

Verification

DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces

This is certainly the most connected DAC I have been to so far. Tweets and connections…

• 2 min read
ESL Market , DAC , wireless , Verification Computing Platform , Virtual System Platform , software virtual prototype , cadence , Acceleration , Functional Verification , Palldium XP , System Design and Verification , System Development Suite , system modeling , embedded software , Rohde & Schwarz , Emulation , dac2012 , LTE , Design Automation Conference , carrier aggregation , LTE advanced

Verification

DAC 2012: High-Level Synthesis Tutorial Standing Room Only

Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing…

• less than a min read
High-Level Synthesis , Intel , C to Silicon , dac2012 , Bohm , SystemC , Synthesis , HLS , ESL , verification

Verification

DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual…

DAC 2012 kicked off yesterday with the annual DAC Reception followed by Gary Smith…

• 3 min read
ESL Market , DAC , Virtual System Platform , software virtual prototype , cadence , Functional Verification , System Design and Verification , Gary Smith EDA , System Development Suite , system modeling , embedded software , GSEDA , dac2012 , Design Automation Conference

Verification

DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development

Change is hard. And we in product marketing for development tools are trying to cause…

• 4 min read
DAC , Virtual System Platform , CDNLive , cadence , debug , Functional Verification , Verum , System Design and Verification , Methods2Business , System Development Suite , system modeling , embedded software , dac2012 , Technology Adoption , Software Generation , Design Automation Conference , Formal verification

Verification

Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced…

• less than a min read
DAC , uvm , uvm world , Functional Verification , UVM 1.1b , Accellera

Verification

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification…

As the EDA industry and its customers are preparing for the yearly show down at the…

• 19 min read
NextOp , DAC , CDNLive , debug , Functional Verification , LeCroy , AMD , System Design and Verification , celeration , Methods2Business , System Development Suite , Xilinx SDK , Incisive , in-circuit emulation , LSI , Palladium XP , Emulation , in-circuit acceleration , Dini , Imperas , ARM , Design Automation Conference , Rohde&Schwarz , DAC breakfast

Analog/Custom Design

What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At…

• 2 min read
DAC , AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , 28nm , 20nm , Advanced Node , Mixed-Signal , mixed signal physical implementation open access , mixed-signal book , mixed signal methodology guide , low-power design , mixed signal , cortex M , mixed-signal design , power , Design Automation Conference , mixed signal implementation , digitally assisted analog , mixed-signal verification

Verification

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San…

• 1 min read
High-Level Synthesis , DAC , TLM , C to Silicon , transaction level , tlm verification , System Design and Verification , TLM design , embedded software , ESLsyn , C-to-Silicon , SystemC , HLS , NASCUG , ESL

Digital Design

Writing More Compact Encounter Scripts with dbGet Expressions

Querying the Encounter database with dbGet is typically pretty concise to begin with…

• 3 min read
dbGet , EDI , Encounter scripts , encounter digital implementation system , expression-based matching , encounter , Digital Implementation , scripting , IC design , tcl

Analog/Custom Design

Cadence To Release the Industry's First Mixed-Signal Methodology Book

The new era of “Internet Everywhere” creates a whole new spectrum of applications…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , analog , Mixed-Signal , mixed-signal book , dac2012 , mixed signal methodology guide , Mixed signal physical implementation , DAC 2012 , mixed-signal design , mixed signal implementation , mixed-signal verification

Verification

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform

There are two choices for how to handle USB devices in a virtual platform. A USB…

• 4 min read
Virtual System Platform , virtual platforms , virtual prototypes , embedded software , USB , Zync-7000 , SystemC , physical USB devices , xilinx , linux , QEMU , System Design and Verification

RF Engineering

Modeling Oscillators with Arbitrary Phase Noise Profiles

When you need to include noisy oscillators in SpectreRF transceiver simulations,…

• 2 min read
RF , RF Simulation , analog/RF , APS , HBnoise , Circuit simulation , RFIC , Virtuoso Spectre , HB , Spectre RF , Analog Simulation , MMSIM , pnoise , phase noise , Virtuoso Spectre Simulator GXL , analog , ADE , Spectre , RF design , harmonic balance , VCO , Oscillator , simulation , noise profiles
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