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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Breakfast Bytes

Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet…

• 3 min read
DAC , ChipEstimate.com , Perspec , pss

System, PCB, & Package Design 

What Is COM /JCOM Channel Compliance All About?

In today’s world of double-digit gigabit-per-second data rates it is imperative that…

• 3 min read
SI , JCOM , Channel Operating Margin (COM) , COM/JCOM , JCOM channel compliance , COM , Channel Operating Margin , Signal Integrity , SystemSI

Breakfast Bytes

"I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine…

• 5 min read
exponential , moore's law , baumol's cost disease

Whiteboard Wednesdays

Whiteboard Wednesdays - What Really Matters When Selecting IP

In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of…

• less than a min read
Whiteboard Wednesdays , IP , SoC Integration

Digital Design

High-Level Synthesis: The Secret Is Out

Gone is the day when companies (our customers) kept their use of high-level synthesis…

• 2 min read
High-Level Synthesis , CDNLive , Stratus , HLS

Breakfast Bytes

Imec on EUV. Are We There Yet?

I already gave an introduction to my first visit to imec in my life in my post If…

• 7 min read
imec , stochastics , EUV

Breakfast Bytes

What's For Breakfast? Video Preview June 18th to 22nd 2018

https://youtu.be/puYFl7m50tM Coming from Dilijian Armenia (camera Gary Bengier…

• less than a min read
rsa conference , rsa , Dolby , millennial , virtual cad , Tensilica , ludwigsburg , dap light

Verification

DMS 2.0 - What's Cool and What's New

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)…

• 1 min read
digital mixed signal , Functional Verification , DMS 2.0 , xcelium simulator

Breakfast Bytes

FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey

Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only…

• 3 min read
FinFET , FD-SOI

Analog/Custom Design

Virtuosity: Let's Have Fun with ADE Debugging – Part 1

Over the years, we have seen our customers’ usage of ICRPs increase dramatically…

• 9 min read
performance , ADE Explorer , ADE L , Virtuoso , ADE-XL , Virtuosity , Simulators , Custom IC Design , ICRP , ADE Assembler

Breakfast Bytes

Why Did EDA Have a Hardware Business Model?

Business models are really important. Just ask any internet startup company that…

• 7 min read
term license , hardware , EDA , cadence cloud

Analog/Custom Design

Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available

The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download…

• 3 min read
IC , ISR20 , ICADV12.3 , ADE , Layout , Virtuoso , Virtuosity , IC6.1.7 , Custom IC Design , Custom IC

Verification

Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic…

• 2 min read
SystemVerilog , uvm , Dynamic Test Load , Functional Verification , xcelium

Breakfast Bytes

Imec Roadmap

I recently visited imec. For an overview of my day, see my earlier post If It's Tuesday…

• 7 min read
nanosheet , stco , 3nm , imec , gaa , FinFET , DTCO

The India Circuit

Indian Airports Go High Tech

No more printed tickets. Shorter queues at check-in counters. Humanoid robots walking…

• 3 min read
Kempegowda International Airport , aadhaar , Airports Authority of India , KIAL , KEMPA , Priyank Kharge

Verification

PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted…

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement…

• 3 min read
controller IP , Verification IP , PCIe Gen4 , PHY , PCIe , PCIe Gen5 , verification

Breakfast Bytes

Heinz Nixdorf's Legacy in Paderborn

I read somewhere that the largest computer museum in the world is the Heinz Nixdorf…

• 6 min read
paderborn , museum , heinz nixdorf museumsforum , nixdorf

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Deliverables Required for Successful SoC In…

In this week’s Whiteboard Wednesday, YJ Patil explains the importance of having a…

• less than a min read
Whiteboard Wednesdays , IP-XACT , Functional Verification , IP integration

Breakfast Bytes

What's For Breakfast? Video Preview June 11th to 15th 2018

https://youtu.be/IYm-CauwKTo Coming from Yerevan Armenia (camera Jack Darrow)…

• less than a min read
dac55 , chipestimate , Raspberry Pi , cloud , baumol's cost disease , FinFET , EUV , FD-SOI
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