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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

SoC and IP

Increased CHI Coherency Verification Challenges

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Dimitry Pavlovsky , Design IP and Verification IP , CHI VIP

Whiteboard Wednesdays

Whiteboard Wednesday—MIPI UniPro for Chip-to-Chip Communications

In this week's Whiteboard Wednesdays video, the last in a three-part series, Kevin…

• less than a min read
Whiteboard Wednesdays , IP , UniPro , communication protocol , MIPI

SoC and IP

Where’s My Star Trek Lifestyle?

The sparkle seems to have gone out of the Internet of Things (IoT) market for the…

• 2 min read
Smarthome , cadence , IP blocks , IoT , wearables , IP design , embedded design , robotics , embedded systems

Verification

Heading Off the Butterfly Effect—The SimVision "Quick Diff"

Functional Verification Debug Blog - SimVision Gems Most engineers are familiar…

• 1 min read
HDL , "butterfly effect" , SimVision waveforms diff , Verilog , SimCompare , VHDL

System, PCB, & Package Design 

What's Good About Using Allegro TimingVision and IPC-2581 to Reduce Design Costs…

This week, you can view a couple of videos where customers describe how they used…

• 1 min read
PCB Layout and routing , Allegro 16.6 , Routing , High Speed , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , DDR3

Analog/Custom Design

Virtuosity: 26 Things I Learned in November and December 2014 by Browsing Cadence…

Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena…

• 4 min read
Liberate AMS , MMSIM , ADE XL , ADE , Virtuoso , Spectre , Analog Design Environment , Virtuosity , PVS , Custom IC Design , Virtuoso Layout Suite , SKILL , IC 6.1.6

System, PCB, & Package Design 

What's Good About Using Sigrity to Gain Signal Access? Check Out This Expert Insights…

This week, you can view a video where a customer describes how they used the Cadence…

• less than a min read
SI , Cadence Design Systems , PCB Signal and power integrity , SPB , Signal Integrity , PCB Signal integrity , Grzenia , SI analysis and modeling

Whiteboard Wednesdays

Whiteboard Wednesdays—ARM AMBA Microcontroller Protocol Family

In this week's Whiteboard Wednesdays video, the first of a two-part series, Avi Behar…

• less than a min read
Whiteboard Wednesdays , CHI , ASB , ATB , APB , AMBA , ARM

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Thieving? 16.6 Has Several New Enhancements…

The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving…

• 1 min read
PCB Layout and routing , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

SoC and IP

HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF

High-performance and high-speed memory design characterized by low-power operation…

• 2 min read
DDR4 , electronic system design , cadence , IP blocks , TSMC , 16nm , FinFET , Hisilicon

SoC and IP

Cadence at CES 2015: Enabling Surreal Surround Sound Audio

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine…

• 1 min read
DTS , Consumer Electronics , cadence , surround sound , audio , Tensilica , HiFi DSP , CES 2015 , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Voltage and Monitoring IP

In this week's Whiteboard Wednesdays, Bob Salem discusses voltage and monitoring…

• less than a min read
IP , voltage and monitoring IP , temperature tracking , intellectual property

SoC and IP

Cadence Firmware Packages Enable Successful IP Integration

Building a system on chip (SoC) from IP blocks requires system-level integration…

• 3 min read
Bring-up , IP integration , ip cores , firmware

SoC and IP

Get a Glimpse at New Ethernet Standards in the Works

I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet…

• 2 min read
25G Ethernet , new Ethernet standards , Ethernet standards , Automotive Ethernet , IEEE 802.3 , ip cores , Ethernet

Verification

Dealing with the "Throw it Over the Wall" Methodology in Power Supply Network De…

"Throw it over the wall" is business slang for completing your part of a project…

• 2 min read
PSN , Power Supply Network , debug , Functional Verification , power-aware , UPF

Verification

Searching Through a Complex Design? DFS to the Rescue!

Recently, while at a customer site, I was faced with the huge task of looking for…

• 4 min read
Functional Verification , simvision , design file search , Incisive Enterprise Simulator (IES)

Whiteboard Wednesdays

Whiteboard Wednesdays—Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applica…

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey…

• less than a min read
Whiteboard Wednesdays , IP , LPDDR4 , 32-bit

SoC and IP

Cadence at CES 2015: Power-Sensitive Always-On Systems

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user…

• less than a min read
audio , power management , HiFi Mini , Tensilica , Realtek Semiconductor , HiFi DSP , CES 2015

Verification

Lazy Test Cases for Tool Failures Using the Testcase Optimizer (TCO)

The Current State It seems to be a fact of life that software has bugs and, unfortunately…

• 7 min read
performance , methodology , verification strategy , debug , tech tips , Incisive , universal verification methodology , verification
CDNS - Fix Layout Hompage