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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Verification

Register for the UVM Register Layer Webinar on January 12!

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim…

• less than a min read
webinar , Doulos , xcelium , uvm register layer

Breakfast Bytes

GLOBALFOUNDRIES 7nm

Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES…

• 3 min read
GlobalFoundries , 7nm , EUV , IEDM

Analog/Custom Design

Automatically Reusing an SoC Testbench in AMS IP Verification

The complexity and size of mixed-signal designs in wireless, power management, automotive…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal solution , analog , Mixed-Signal , analog/mixed-signal , Virtuoso environment , mixed-signal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)

Enabling Constraint-Driven Design With the pre-layout testbench built, populated…

• 5 min read
Serial link analysis , SI , Constraint Driven Design , Multi-Gigabit , PCIe , Signal Integrity , Sigrity

Breakfast Bytes

CES18 Preview

It's the start of a new year and that means it is the Consumer Electronics Show in…

• 9 min read
ces 2017 , deep learning , CES , audio , inception , atmos , Dolby , Tensilica , vision , neural networks

Breakfast Bytes

What is Meltdown? How Can It Affect Both Intel and Arm?

If you pay attention to anything to do with processors, security, or even investment…

• 8 min read
security , Intel , meltdown , x86 , ARM

Breakfast Bytes

What's For Breakfast? Video Preview January 8th to 12th 2018

https://youtu.be/txCnT3N4OSY Coming from Executive Briefing Center (camera Sean…

• less than a min read
Consumer Electronics Show , CES , CES2018 , semi , Virtuoso , ARM

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (3 of 8)

IBIS-AMI Modeling With initial PCB trace and via models in place for our hypothetical…

• 2 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Gary Patton on GF, IBM, 7nm, EUV, and More

At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss…

• 8 min read
fab8 , 7lp , 12fdx , gf , gary patton , malta , 12lp , GlobalFoundries , 7nm

The India Circuit

Face Recognition and Hackathon: An Unlikely and Innovative Combination

Happy New Year! While most other folks are just easing back to work, those of us…

• 4 min read
VLSI & Embedded Systems Design Conference , Tensilica , Tensilica Xtensa , neural networks , CNN , face recognition

Breakfast Bytes

Intel 10nm

At IEDM last month, Intel announced details of their 10nm process. Later the same…

• 5 min read
Intel , coag , FinFET , 10nm , Breakfast Bytes

Breakfast Bytes

Frankenstein

"Hail to thee, blithe spirit! Bird thou never wert"...and Frankenstein. What do these…

• 3 min read

Breakfast Bytes

What's For Breakfast? Video Preview January 1st to 5th 2018

https://youtu.be/Xja6H1meqac Coming from Yosemite National Park (camera Carey…

• less than a min read
Intel , ces 2017 , Consumer Electronics Show , CES , GlobalFoundries , 7nm , 10nm

Breakfast Bytes

Why Don't Planes Obey Moore's Law?

In my post about Silexica ( Silexica: Mastering Multicore ) I said that I like to…

• 9 min read
great flight diagram , aeronautics , tennekes , flight , simple science of flight

Analog/Custom Design

Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

“The reason birds can fly and we can't is simply because they have perfect faith…

• 2 min read
Cadence blogs , Virtuoso , RF design , Virtuosity , Virtuoso Video Diary , CPG Technical Communications Engineering

Breakfast Bytes

Blue LEDs, Nobel Prizes, and IEDM Keynote

At IEDM last week, for the first time, there was a second plenary session (awards…

• 6 min read
gallium nitride , nobel prize , Wally Rhines , LED , blue led , gan , IEDM

Breakfast Bytes

Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens

OK, that wins the prize for best title of a presentation in the recent RISC-V workshop…

• 11 min read
risc-v , celerity , boom , picochip , risc-v foundation , esperanto , sifive

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar explains the behavioral differences…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

RISC-V Workshop, Milpitas

The latest semi-annual RISC-V workshop took place the week after Thanksgiving. The…

• 8 min read
Western Digital , risc-v , celerity , boom , picochip , risc-v foundation , esperanto , 16nm , 7nm
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