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Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
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Blog - Post List

Latest blogs

Breakfast Bytes

China Bike Rental

In the last couple of years, one of the biggest changes in China has been the arrival…

• 9 min read
China , uber , lyft , bicycle , mobile , mobike , ofo

Analog/Custom Design

Virtuosity: Signal Browsing Gets Easier with Advanced Search Options

Imagine what would happen if we were living in the world with no search engines.…

• 4 min read
ViVa-XL , custom/analog , Virtuoso Analog Design Environment , ViVA , Virtuosity , Circuit Design , Custom IC Design , Custom IC

Whiteboard Wednesdays

Whiteboard Wednesdays - The 3 Methods of Memory Controller Port Arbitration

In this week's Whiteboard Wednesdays video, Jing Liu describes three methods of port…

• less than a min read
DDR Controller , Port Arbitration , Whiteboard Wednesdays

Breakfast Bytes

What's For Breakfast? Video Preview March 19th to 23rd 2018

https://youtu.be/2-ErrC9yy2k Coming from SEMICON China, Shanghai (camera Tracy…

• less than a min read
semicon , semiconductor equipment , semicon china , licklider , EDA

Verification

Preparing Accellera Portable Stimulus Standard for Ratification

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process…

• less than a min read
pswg , Perspec , perspec system verifier , pss , portable stimulus

Breakfast Bytes

The Great Firewall of China

This is a continuation of yesterday's post on Walled Gardens . Arguably the greatest…

• 9 min read
China , Facebook , vpn

Breakfast Bytes

Walled Gardens

I'm in China this week, for SEMICON China, along with 70,000 of my closest friends…

• 4 min read
China , aol , google , Facebook , censorship , great firewall of china

Verification

Temporals, Reset, and Test Phases

One of the biggest challenges in dynamic functional verification is testing Reset…

• 4 min read
Specman , UVM e , Specman e , e , e language

System, PCB, & Package Design 

Thermal Analysis of Package/PCB Systems: Challenges and Solutions

More and more package/PCB system designs are requiring thermal analysis. Power dissipation…

• 3 min read
PCB , PI , Power Integrity , Voltus , electrical-thermal co-simulation , thermal , PowerDC

Breakfast Bytes

Spanish Flu Is 100 Years Old on Sunday

This Sunday, March 11, is the 100th anniversary of the outbreak of Spanish flu in…

• 6 min read
spanish flu , h7n4 , flu virus , h1n1

Analog/Custom Design

Virtuosity: Exploring Histories

OK we heard you, you want to be able to specify Virtuoso ADE Explorer history names…

• 3 min read
ADE Explorer , ADE , Virtuosity , ADE Assembler

Analog/Custom Design

Virtuosity: Do I Need To Run a Simulation To Plot From a Text File?

You'll be glad to hear the answer is No! In Virtuoso Visualization and Analysis,…

• 2 min read
Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ViVA , Virtuosity , Assembler , ADE Assembler

Breakfast Bytes

embedded world: Mark Papermaster of AMD

The opening keynote from embedded world in Nuremberg was by Mark Papermaster, who…

• 4 min read
epyc , Automotive , ryzen , AMD , Embedded World

Breakfast Bytes

3nm Cadence and imec

I started Breakfast Bytes on October 8, 2015, my first day back at Cadence. The very…

• 4 min read
Genus , testchip , 3nm , imec , Innovus , 5nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Error Correction Code Implementations in Memory Controller…

In this week's Whiteboard Wednesdays video, Jing Liu provides a simple explanation…

• less than a min read
DDR Controller , Whiteboard Wednesdays , ECC

Verification

App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For Y…

Welcome to another App Note Spotlight! One of the biggest issues facing verification…

• 2 min read
incremental elaboration , Flows , Functional Verification , MSIE

Breakfast Bytes

Spectre with a Red Hat, part 2

This is the second post about Red Hat's John Masters presentation at FOSDEM 2018…

• 6 min read
red hat , Spectre , jon masters , linux

Breakfast Bytes

Spectre with a Red Hat

A couple of weekends ago it was FOSDEM 2018, the largest conference on open source…

• 8 min read
security , meltdown , Redhat , Spectre , linux

The India Circuit

Incubators, Accelerators and Fabless Chip Design at IESA Vision Summit 2018

This week we had one of the Indian semiconductor industry’s biggest and most well…

• 6 min read
Vision Summit , Government of Karnataka , fabless chip , IESA , India Electronics and Semiconductor Association , Priyank Kharge , semiconductor incubator
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