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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Verification

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition…

• 1 min read
AF , uvm , Specman , methodology , Testflow , Functional Verification , testflow phase debugging , testflow phases , advanced verification , e language , blocking activities , IES-XL

Analog/Custom Design

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

• 3 min read
mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Digital Design

Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation…

As you know, Cadence Online Support is your 24/7 site for getting help and resolving…

• 2 min read
SoC-Encounter , Cadence On-Line Support , Low Power , Foundation Flow , DBTcl , EDI system , Signoff Analysis , Low-Power , EDI 11.1 , Cadence Online Support , NanoRoute , Silicon Realization , Digital Implementation , EDI system Encounter Digital Implementation System , CTS , Enouter Timing System , Rapid Adoption Kits , RAKs , SoC-Encounter dbGet dbSet

Verification

Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded…

• 2 min read
AF , Specman , new features , Functional Verification , licenses , license search , Incisive , e language , Specman licenses , verification , IES-XL

Verification

Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq…

• 5 min read
Virtual System Platform , zynq , virtual platforms , TLM , posedge , IP-XACT , Henry Von Bank , virtual prototypes , VSP , RDF , SystemC , xilinx , ARM , FFT , Zynq virtual platform , Zynq-7000

System, PCB, & Package Design 

What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

This week, I'm providing a very short blog. While the content is brief and simple…

• less than a min read
capture , "capture CIS" , OrCAD Capture Marketplace , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Entry , SPB16.5 , PCB Capture , Schematic

Verification

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional…

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University…

• 1 min read
DAC , uvm , Joe Hupcey III , interview , Functional Verification , video , Dr. Kerstin Eder , University of Bristol , DAC 2012

Verification

C-to-Silicon Japan User Group and Ikegami Production Experience

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level…

• 2 min read
High-Level Synthesis , customers , Maesato , japan , Japan user group , Ikegami , SystemC , C-to-Silicon Compiler , Synthesis , Virtex-6 , HLS , ESL , FPGA

Verification

DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

It is nice to see when visions get closer to reality. When Cadence announced its…

• 4 min read
DAC , Virtual System Platform , zynq , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , Emulation , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

Verification

Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

Readers of this blog and of Team Specman will recall that Integrated Development…

• less than a min read
DAC , eclipse , Joe Hupcey III , Cristian Amitroaie , DVT , AMIQ , DAC 2012 , RTL design , integrated development environment , IDE

Verification

SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impac…

One of the most interesting concepts in SystemC TLM-2.0 is the concept of Direct…

• 4 min read
Direct Memory Interface , Zynq-7000' , SystemC , Virtual Platforms , linux

Verification

DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre…

• 3 min read
RPP , FPGA Based Prototyping , Custom FPGA Boards , hardware/software integration , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , JTAG , Emulation , virtual prototype , Software Development and Debug , xilinx , DAC 2012 , HAPS , John Blyler , Design Automation Conference , system integration , FPGA

System, PCB, & Package Design 

Shocking Rules and Material Remove ESD Risk in Allegro PCB Smartphone Designs

Static electricity can send shocks through your body. We have all experienced walking…

• 2 min read
PCB , VSD , shock , Team Allegro , electrostatic discharge , electric shock , XStatic , ESD protection , Shocking Technologies , SPB , smartphones , Allegro , ESD

Verification

DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System…

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically…

• less than a min read
DAC , Joe Hupcey III , interview , debug , video , SoC , Mike Stellfox , DAC 2012 , verification

Verification

DAC 2012: Enabling the Programming of an Extensible Processing Platform

We at Cadence have been writing about the virtual prototype associated with the Xilinx…

• 6 min read
DAC , Virtual System Platform , cadence , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

Verification

High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump…

Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis…

• 3 min read
DAC , TLM , DAC panel , high-level verification , RTL , Forrest Gump , high-level design , SoC , System Design & Verification , SystemC , C-to-Silicon Compiler , high level synthesis , HLS , C++ , ESL , verification

Digital Design

EDI System’s get_metric Command Makes Metrics Reporting Quick and Easy

In this blog post I want to highlight the command get_metric that was introduced…

• 3 min read
get_metric , SoC-Encounter , cadence.com community , cadence , EDI system , EDI 11.1 , Cadence Online Support , encounter , EDI 10.1 , Digital Implementation , Encounter Digital Implementation , SoC Realization , EDI 11 , "SoC-Encounter"

Verification

Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video

Continuing our conversation on leveraging social media for EDA, at the Design Automation…

• 1 min read
Brian Fuller , Joe Hupcey III , interview , video , Blogging , Social Media , DAC 2012 , EE Times

Verification

Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners…

• 1 min read
DAC , Joe Hupcey III , ABV , Functional Verification , bugs , NVIDIA , formal , Vigyan Singhal , Oski Technology , assertions , DAC 2012 , IEV , Formal verification , IFV , verification , Assertion-based verification
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