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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

The India Circuit

Beyond Robots and Jetpacks at the Society of Women Engineers Conference in Pune

This event happened a while ago, but I thought it was still topical enough to blog…

• 2 min read
pune , bengaluru , we local , society of women engineers , grace hopper conference , bangalore , India

Analog/Custom Design

Virtuosity: Loading Complete 'Routing Recipes' with a Single Click

Have you checked out the new VSR Preset feature and the related forms in the IC6…

• 6 min read
automatic routing , resetting preset options , Virtuoso Space-based Router , preset file , vsrSavePreset , running SKILL in a VSR preset , VSR Delete Preset , loading a preset file , vsrLoadPreset , VSR Preset , Virtuosity , deleting a preset file , VSR Save Preset , vsrDeletePreset , saving a preset file , preset options , VSR Load Preset , VSR preset SKILL , Reset VSR Options

Breakfast Bytes

Discovery of the Electron

Today is the 120th anniversary of the discovery of the electron by J.J. Thomson in…

• 6 min read
nobel prize , electron , Einstein , j.j. thomson , thomson , Breakfast Bytes

Verification

How to Model State Machines in the Accellera Portable Stimulus Standard for Low Power…

The Accellera Portable Stimulus Standard (PSS) is experiencing growing customer interest…

• less than a min read
Low Power , SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Breakfast Bytes

Computer History Museum History

The Computer History Museum (CHM) is on Shoreline Boulevard in Mountain View in one…

• 5 min read
computer history museum , chm , gwen bell , Breakfast Bytes , Gordon Bell

Analog/Custom Design

Virtuosity: The New Virtuoso ADE Product Suite - Knowledge Resource Kit

Cadence introduced its new set of Virtuoso® ADE products, which includes Virtuoso…

• 4 min read
Analog Design Environment , ADE Explorer , Explorer , Rapid Adoption Kit , Analog Simulation , ADE , Mixed-Signal , welcome kit , knowledge resource kit , Virtuoso Analog Design Environment , Virtuoso , Spectre , Analog Design Environment , Virtuosity , mixed signal , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

O Lord, Won't You Buy Me a Mercedes Benz...Truck

You hear a lot of talk about autonomous cars, but I've also heard many times that…

• 5 min read
autonomous trucks , mercedes-benz , convoying , Breakfast Bytes

Breakfast Bytes

An Academic View on How Tesla Will Not Win

Professor Markus Lienkamp, of Technische Universität München (roughly the MIT of…

• 8 min read
Automotive , German OEMs , Markus Lienkamp , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to Cadence USB Type-C VIP

In this week's Whiteboard Wednesdays video, Asila Nahas describes the USB Type-C…

• less than a min read
Verification IP , Whiteboard Wednesdays , USB Type-C , VIP , USB , Type-C

Breakfast Bytes

BROADPWN: Attacking Smartphones through the Wi-Fi Chip

Do you have an iPhone? Did it suddenly update IoS at the end of last week? That's…

• 7 min read
aslr , dep , virus , android , Mobile World Congress , iOS , worm , broadpwn , malware

Breakfast Bytes

What's For Breakfast? Video Preview August 7th to 11th 2017

https://youtu.be/uIodpPVnsXM Coming from Cadence cafeteria patio (camera Sean…

• less than a min read
Automotive , 3d logic , electron , london science museum , bletchley park , Samsung , transistor , lithium ion , 3d nand flash , samsung sdi , battery

SoC and IP

Happy Birthday Tensilica

Yes, it’s Tensilica’s birthday! Twenty years ago today, on July 31, 1997, Tensilica…

• 2 min read
DSP , Chris Rowen , HiFi , Tensilica , vision

Breakfast Bytes

Tensilica Has the Same Birthday as Harry Potter

You probably know that Harry Potter's birthday is July 31st. As it happens, that…

• 5 min read

Analog/Custom Design

Virtuosity: Handy UI Enhancements in ADE Assembler & ADE Explorer

We have been busy working on several small UI enhancements for Assembler & Explorer…

• 4 min read
Analog Design Environment , ADE Explorer , Explorer , ADE , Virtuoso , Analog Design Environment , Virtuosity , Custom IC Design , ADE Assembler

Verification

X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset

All chips need to cold reset on every power-up. Warm resets, however, are a bit more…

• 2 min read
SystemVerilog , Functional Verification , xcelium , Reset , simulation

Breakfast Bytes

The Intel Museum

During the summer, while the living is easy and the fish are jumping, each Friday…

• 3 min read
Intel , business plan , microprocessor , Breakfast Bytes , intel museum

Verification

Moving to Xcelium Simulation? I’m Glad You Asked

Ready to take the next step in simulation technology with a true third-generation…

• 2 min read
performance , Self-Help , uvm , simvision , RAK , Multi-Core , Appnote , troubleshooting , simulation , Cadence support

Breakfast Bytes

Secret Key Generation with Physically Unclonable Functions

Yesterday, I wrote about automotive security from a big-picture level. Today let…

• 4 min read
trng , physically unclonable function , puf , aes , prng.trivium , rijndael , Breakfast Bytes

Verification

ROHM CO., Ltd Adopts Our Functional Safety Verification Solution

On July 17, 2017, Cadence announced that the Cadence® Functional Safety Verification…

• less than a min read
functional safety , Functional Verification , ROHM Co. , press release , ISO 26262
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