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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuoso Studio IC 23.1: Using Net Tracer for Design Review

This blog explores how Virtuoso Studio Net Tracer can help you perform a design review…

• 4 min read
IC 23.1 , Analog Design Environment , Cadence blogs , Virtuoso Studio , custom/analog , cadence , review , design review , analog , Virtuoso RF , Layout EXL , training , Layout Suite , Virtuoso Analog Design Environment , training bytes , Layout , Virtuoso , design , Virtuoso Video Diary , Analog Layout Automation , Analog Layout , Custom IC Design , Net Tracer , Virtuoso Layout Suite , Custom IC , blog

SoC and IP

How Cadence Is Revolutionizing Automotive Sensor Fusion

The automotive industry is currently on the cusp of a radical evolution, steering…

• 5 min read
Automotive , Sensor Processing , sensor fusion , Automotive SoC , automotive IP , NPU , AI

Verification

Root Cause Your Regression Failures Faster with Verisium PinDown

Use Verisium Pindown to identify the specific code commits that caused your regression…

• 2 min read
Functional Verification , verisium , pindown , codeminer , AI , waveminer

Analog/Custom Design

Start Your Engines: The Innovation Behind Universal Connect Modules (UCM)

Read this blog to know more about the innovation behind Universal Connect Modules…

• 6 min read
SystemVerilog , Start Your Engines , Spectre AMS Designer , Verilog-AMS , Mixed-Signal , mixed-signal verification

Verification

Evolution of AMBA CHI Protocol: Introducing Issue G Update

After the significant CHI Issue F update that introduced a number of important new…

• 2 min read
CHI Issue G , VIP , AMBA , CHI VIP , verification

Life at Cadence

Forging Connections Ignites Allyship

Allyship in the workplace is becoming increasingly important to building and sustaining…

• 3 min read
featured , DEI , LifeAtCadence , DEIatCadence

Life at Cadence

The Impact of the Talent Pipeline Program (TPP) on My 5-Year Journey at Cadence

The Talent Pipeline Program (TPP) at Cadence Design Systems has been a pivotal element…

• 2 min read

Verification

Mastering Triage in Verisium Manager: A Complete Guide

In today's complex verification environments, managing debug tasks efficiently is…

• 2 min read
debug , Triage , Regression , Verisium Manager

Computational Fluid Dynamics

Profiles in CFD with Guillaume Martinat

The Profiles in CFD series aims to provide insights into the latest trends and projects…

• 4 min read
Flying Whales , Profiles in CFD , Fidelity Fine Marine , simulation software , Cadence Fine Marine

Verification

Unravelling L0p Updates on the PIPE Interface

Power saving is an important aspect in PCIe devices and to leverage this, PCIe 6…

• 5 min read
Verification IP , pcie gen6 , PCIe 6.0 , l0p

Digital Design

All EVs Need the Midas Functional Safety Platform

A more appropriate title for this blog could be “All Vehicles with ADAS Need the…

FormerMember • 2 min read
conformal , Genus , functional safety , midas , Digital Implementation , Innovus

Verification

Demystifying Verification of PCIe 6.0 Equalization

The PCI-SIG Developers Conference 2024 is poised to be the premier event for professionals…

• 6 min read
Verification IP , equalization , PCIe , PCIe 6.0 , Training Sequences

Digital Design

Online Course: Start Learning About 3D-IC Technology

Designing 3D-ICs with integrity involves a commitment to ethical practices, reliability…

• 2 min read
Integrity 3D-IC Platform , 3D-IC , 2.5DiC , Digital Implementation , Innovus , moore's law , 3D-IC Technology , heterogenous integration , Allegro , system planner

Verification

Verification Using Near End Loopback

Near End Loopback (NELB) is a feature introduced by Intel's PHY Interface spec revision…

• 2 min read
Verification IP , NELB , PHY DUT

Data Center

How Data Centers Can Make AI Greener

As the world increasingly turns to artificial intelligence (AI) for its vast potential…

• 3 min read
CFD , featured , Reality , digital twin , Computational Fluid Dynamics , thermal

Artificial Intelligence (AI)

AI-Generated Constraint Methodology for PCB and IC Package Design Teams

It is well-known that constraint-driven designs are correct from the outset and adhere…

• 5 min read
PCB , featured , SoC , Constraint Methodology , AI/ML

Data Center

Short-Term Fixes and Data Center Underutilization

Short-term solutions in data centers can create more problems than they solve. These…

• 2 min read
data center , digital twin , Cadence Reality DC

Spotlight Taiwan

加速智慧系統設計 - CadenceCONNECT Taiwan 8 月 22 日 (四) 隆重登場!

加速智慧系統設計 Cadence打造更美好世界Accelerating Intelligent System Design : A Better World Designed…

• less than a min read
dynamic duo , Automotive , MSA , 3D-IC , cerebrus , digital twin , Virtuoso , taiwanese blog , CadenceCONNECT Taiwan

Digital Design

Training Bytes: Explore Cadence DFT Synthesis Flow with Bytes

Training Bytes are not just short technical videos; they are particularly designed…

• 4 min read
DFT , Modus DFT , IEEE 1500 , Genus Synthesis Solution
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