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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: RTFM

Wait, don't run away! In this case I really mean " Read The Fantastic Manual ". A…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Comment Direct From XJTAG, Ltd.

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their…

• 2 min read
DAC , Functional Verification , XJTAG

Verification

Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 6 min read
IntelliGen , Specman , debug , Functional Verification , e , AOP , IES-XL

Verification

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System…

One of the great things about DAC is the opportunity to meet new people and find…

• 2 min read
DAC , System Design and Verification , Incisive , SoC , Marvel

Verification

Survey Results and Commentary on The XJTAG Girls at DAC 2009

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls…

• 7 min read
DAC , Functional Verification , OVM , XJTAG

System, PCB, & Package Design 

What's Good About Blogging? - The People: Readers, Posters, Cadence!

I'm taking a break this week from the technical type posts to say THANK YOU to the…

• 2 min read
IC Packaging and SiP Design , PCB design , FPGA

Verification

More Details on Post Silicon Embedded Software Verification With ISX

Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in…

• 3 min read
AXI , eVC , System Design and Verification , OVM , SoC , ISX , ARM , ESL , FPGA

Digital Design

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about…

• 1 min read
SoC-Encounter , Cadence SiP , Co-Design , Digital Implementation , FlipChip

Verification

Slides From DAC Virtual Platform Workshop

As a follow-up to my report on the DAC Virtual Platform Workshop I would like to…

• less than a min read
DAC , virtual platform , System Design and Verification

System, PCB, & Package Design 

What's Good About DEHDL Usability Improvements? The Secret's in the SPB16.2 Release

The Design Entry HDL (DEHDL) usability improvements are many and significant in the…

• 5 min read
SPB 16.2 , DEHDL , PCB design , Allegro

Digital Design

Useful dbGet One-Liners

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet…

• 2 min read
dbGet , dbSet , Digital Implementation

System, PCB, & Package Design 

Power Issues? Manage Your IR Drop The "Advanced" Way

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written…

• less than a min read
16.01 , PCB Layout and routing , SPB 16.2 , PCB Signal and power integrity , Allegro 16.2 , SPB16.2 , PCB design

Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

Analog/Custom Design

We Interrupt Your Regularly Scheduled Programming...

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso…

• 1 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype

SoC and IP

Reflections on Life and Death in the Memory Sector: Spansion and Qimonda, Long on…

Hammered by market events, two significant memory suppliers suffer in Chapter 11…

• 6 min read

Verification

Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle…

Being a Brit, Cricket is never very far from my thoughts especially when travelling…

• 2 min read
Intel , Low Power , System Design and Verification , embedded software , ARM

Digital Design

5 Fascinating People I Met at the 2009 Design Automation Conference

As much as the Design Automation Conference (DAC) is about demonstrating solution…

• 5 min read
DAC , Digital Implementation
CDNS - Fix Layout Hompage