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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Post-DAC 2009 Survey on The XJTAG Girls

One non-technology item that received an extraordinary buzz at DAC 2009 were the…

• 1 min read
DAC , Functional Verification

Verification

1st Ever Virtual Platform Workshop Deemed a Success

Yesterday DAC hosted the first ever Virtual Platform Workshop , a full day dedicated…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification

System, PCB, & Package Design 

What's Good About Cavity Support in APD? You'll see for yourself using the SPB16…

No - we're not talking teeth, candy, and cavities here ... Many customers have been…

• 3 min read
SPB 16.2 , APD , PCB design

Verification

Finding the Opportunities in ESL

I came to DAC 2009 looking for the industry trends in ESL, because as we all know…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification , ESL High Level Synthesis

Verification

Day 1 of DAC is a Wrap

Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis…

• 3 min read
DAC , TLM 2.0 , System C , OSCiI , System Design and Verification

Analog/Custom Design

Things You Didn't Know About Virtuoso: Customizing the Library Manager

I've told you in previous postings about some new features in Virtuoso IC6.1 which…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Customer Questions About TLM-driven Design and Verification

In the latest blog published by Ron Wilson there were two questions about our TLM…

• 1 min read
System Design and Verification , TLM 2.0 , System C , C-to-Silicon , high level synthesis

Verification

DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able…

• 1 min read
DAC , IntelliGen , Specman , Functional Verification , simvision , OVM e , e , SystemC , IES-XL

SoC and IP

Rethinking SSDs?

NAND Flash's SSD Vision: Wholesale replacement of HDDs by SSDs in the huge market…

• 7 min read

Verification

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some…

• 1 min read
SystemVerilog , debug , Functional Verification , simvision , Verilog , IES

Digital Design

Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and…

I'm looking forward to heading out to San Francisco next week for the 46th Design…

• 1 min read
DAC , Digital Implementation , Cadence InCyte Chip Estimator , Encounter Digital Implementation System 8.1

Verification

DAC '09 for the Specmaniac

The following are the "must see" items for Specmaniacs lucky enough to get travel…

• 3 min read
DAC , Specman , Functional Verification , OVM e , e , Mike Stellfox , Jason Andrews

System, PCB, & Package Design 

What's Good About Allegro's Placement Application Mode? - Look to SPB16.2 and See

In prior releases, Allegro PCB Editor does not provide the user the ability to place…

• 5 min read
Allegro 16.2 , PCB Editor , PCB design

Verification

At DAC Next Week

Yours truly will be at the big show next week, and I hope that all of you in the…

• 1 min read
DAC , Specman , Functional Verification , OVM , OVM e , DVcon

Verification

Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage…

• 2 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

Verification

It's DAC Time Again!

By now, you've probably seen that Cadence is participating quite heavily in DAC this…

• 2 min read
DAC , Functional Verification , verification

Verification

Specman And The Cadence ESL+TLM News

Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification…

• 2 min read
IEEE 1647 , DAC , Specman , TLM , Verification methodology , Functional Verification , simvision , OVM e , e , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , ESL , AOP , IES-XL

Analog/Custom Design

DesignCon 2010 Call for Papers

Hello, As a member of the technical committee and as the chair member for the Analog…

• less than a min read
DesignCon , Advanced Node , Mixed-Signal , RF design , mixed signal , Custom IC Design

Verification

What is Next for SystemC?

Let your voice be heard at the North American SystemC Users Group interactive Town…

• 1 min read
TLM , System Design and Verification , OSCI , SystemC , high level synthesis , HLS
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