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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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System, PCB, & Package Design 

Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting…

Manufacturability and quality of the power and ground feeds for your package are…

• 2 min read
SiP , IC Package , 16.6 , APD , package design , Allegro Package Designer

Verification

New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog…

There is always a demand for learning something simply and quickly on your own in…

• 3 min read
SystemVerilog , Verification IP , uvm , GMII , Rapid Adoption Kit , VIP , M-PCIe , RAK

Whiteboard Wednesdays

Whiteboard Wednesdays - Defining Different Types of USB Controllers

In this week's Whiteboard Wednesdays, Jacek Duda takes a closer look at different…

• less than a min read
Whiteboard Wednesdays , host , bus , USB controllers , peripheral devices , hub

SoC and IP

Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since…

• 1 min read
PCIe controller , PCIe IP , PCIe low power , PCIe , PCIe PHY

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

Cadence Online Support, https://support.cadence.com/ , provides access to support…

• 5 min read
COS , IMC , SystemVerilog , random stability , LPS , UVM-ML , CPF , debugging tips , Cadence Online Support , UVM ML , troubleshooting , irun , IES , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6…

Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region…

• less than a min read
constraint region , Allegro 16.6 , SPB , PCB Editor , BGA , Layout

Whiteboard Wednesdays

Whiteboard Wednesdays - Get to Know 802.11a/c Wireless Analog Front End Solution

In this week's Whiteboard Wednesdays, Priyank Shukla discusses Cadence's wireless…

• less than a min read
Whiteboard Wednesdays , wireless AFE , 802.11a/c , analog front end , AFE

SoC and IP

Ethernet in Cars - The Next Big Thing for Ethernet

Ethernet is coming to cars. Cars now have rear-view cameras and infotainment systems…

• 2 min read
CDNLive , Automotive Ethernet , automotive electronics , broadcom , Ethernet , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays - See How Customizable Processors Can Help to Offload Your…

In this week's Whiteboard Wednesdays, we take a little different approach and show…

• less than a min read
Whiteboard Wednesdays , IP , customizable processors , Tensilica , offload application processor

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Dual-Side Contact Components? It’s in the 16…

The use of dual-sided contact components when placed on internal layers of the PCB…

• 3 min read
PCB Layout and routing , Allegro GUI , inset vias , Allegro 16.6 , Routing , staggered vias , layer stacks , SPB , PCB Editor , PCB routing , Layout , via , PCB design , Allegro PCB Editor , buried vias , HDI , PCB Capture

Analog/Custom Design

EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia…

• 2 min read
DAC , Carnegie Mellon University , EDA , memory circuit yield , Semiconductor , university program

Whiteboard Wednesdays

Whiteboard Wednesdays - Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesdays, Mukul Dawar explains the NVM Express protocol…

• less than a min read
Verification IP , Whiteboard Wednesdays , Functional Verification , verifiying SSDs , verifying solid state drives , NVM Express protocol

Analog/Custom Design

Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online …

Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40…

• 4 min read
Variability Aware Design , ADE GXL , VSR , Routing , ADE XL , Layout , Spectre , Analog Design Environment , Placement , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification…

• 2 min read
AF , Specman , debug , vr_ad , e code , Funcional Verification , Incisive Enterprise Simulator (IES) , ipxact

Whiteboard Wednesdays

Whiteboard Wednesdays - Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays, Moshik Rubin discusses the history of the PCI…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PCI Express

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Design Partitioning? 16.6 Has Several New Enhancements

The 16.6 release of Allegro PCB Editor has several new enhancements for team design…

• 3 min read
Allegro 16.6 , 16.6 , Team design , SPB , PCB Editor , Constraint Manager , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays - Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays, Jacek Duda follows up on his earlier video…

• less than a min read
USB IP controllers , Whiteboard Wednesdays , USB controllers

Whiteboard Wednesdays

Whiteboard Wednesdays—Improving Power Optimization with PCI Express

In this week's Whiteboard Wednesdays video, Arif Khan takes a closer look at PCI…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express , power optimization

System, PCB, & Package Design 

What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6 Has It

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to…

• 10 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , layer stacks , artwork , SPB , interfaces , PCB Editor , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Standards based Interfaces , Allegro
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