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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Verification

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification…

As the EDA industry and its customers are preparing for the yearly show down at the…

• 19 min read
NextOp , DAC , CDNLive , debug , Functional Verification , LeCroy , AMD , System Design and Verification , celeration , Methods2Business , System Development Suite , Xilinx SDK , Incisive , in-circuit emulation , LSI , Palladium XP , Emulation , in-circuit acceleration , Dini , Imperas , ARM , Design Automation Conference , Rohde&Schwarz , DAC breakfast

Analog/Custom Design

What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At…

• 2 min read
DAC , AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , 28nm , 20nm , Advanced Node , Mixed-Signal , mixed signal physical implementation open access , mixed-signal book , mixed signal methodology guide , low-power design , mixed signal , cortex M , mixed-signal design , power , Design Automation Conference , mixed signal implementation , digitally assisted analog , mixed-signal verification

Verification

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San…

• 1 min read
High-Level Synthesis , DAC , TLM , C to Silicon , transaction level , tlm verification , System Design and Verification , TLM design , embedded software , ESLsyn , C-to-Silicon , SystemC , HLS , NASCUG , ESL

Digital Design

Writing More Compact Encounter Scripts with dbGet Expressions

Querying the Encounter database with dbGet is typically pretty concise to begin with…

• 3 min read
dbGet , EDI , Encounter scripts , encounter digital implementation system , expression-based matching , encounter , Digital Implementation , scripting , IC design , tcl

Analog/Custom Design

Cadence To Release the Industry's First Mixed-Signal Methodology Book

The new era of “Internet Everywhere” creates a whole new spectrum of applications…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , analog , Mixed-Signal , mixed-signal book , dac2012 , mixed signal methodology guide , Mixed signal physical implementation , DAC 2012 , mixed-signal design , mixed signal implementation , mixed-signal verification

Verification

Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform

There are two choices for how to handle USB devices in a virtual platform. A USB…

• 4 min read
Virtual System Platform , virtual platforms , virtual prototypes , embedded software , USB , Zync-7000 , SystemC , physical USB devices , xilinx , linux , QEMU , System Design and Verification

RF Engineering

Modeling Oscillators with Arbitrary Phase Noise Profiles

When you need to include noisy oscillators in SpectreRF transceiver simulations,…

• 2 min read
RF , RF Simulation , analog/RF , APS , HBnoise , Circuit simulation , RFIC , Virtuoso Spectre , HB , Spectre RF , Analog Simulation , MMSIM , pnoise , phase noise , Virtuoso Spectre Simulator GXL , analog , ADE , Spectre , RF design , harmonic balance , VCO , Oscillator , simulation , noise profiles

Analog/Custom Design

Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and…

• 4 min read
inherited connections , EDI , Low Power , mixed signal solution , CPF , analog , Mixed-Signal , encounter , Verilog , mixed signal physical implementation open access , Virtuoso , oa , Mixed signal physical implementation , mixed signal , OA: OpenAccess , mixed-signal design , Virtuoso environment , mixed signal implementation , design implementation , Common Power Format

Analog/Custom Design

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

This post isn't directly about tips and tricks for getting the most out of Virtuoso…

• 1 min read
Virtuoso IC6.1.5 , Rapid Adoption Kit , workshop , analog , Constraint-driven , Virtuoso , ViVA , Connectivity-driven , Custom IC Design , RAKs , Virtuoso Layout Suite XL

System, PCB, & Package Design 

What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to…

Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro…

• 2 min read
PCB , PCB Layout and routing , IC Packaging , packaging , visability , APD , Allegro 16.5 , PCB Editor , Allegro Package Designer , advanced package designer , design , PCB design , bond wires , SPB16.5 , color visibility , wirebond color , Allegro

Verification

Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros…

• 4 min read
AF , Specman , Functional Verification , Incisive , e language , define-as , writing macros , macros , testbench , simulation , verification

RF Engineering

Measuring 2-Tone Intermodulation Using Envelope-Following Analysis

From time to time, SpectreRF users simulate very large, extracted-view circuits in…

• 4 min read
RF , RF Simulation , analog/RF , envelope , RFIC , HB , Spectre RF , spectre spectreRF , RF designer , Analog Simulation , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , fast envelope , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , RF design , harmonic balance , SpectreRF tutorials , simulation , wireless integrated circuit verification

Analog/Custom Design

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should…

• 3 min read
ECO , Static timing analysis , EDI , mixed signal design , parasitic , IC 6.1 , mixed signal solution , Open Access , STA , timing model , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , EDIS , ECOs and PCells , Mixed signal physical implementation , mixed signal , signoff , OpenAccess , Virtuoso environment , mixed signal implementation

Verification

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products…

• 5 min read
DAC , CDNLive , Acceleration , debug , Functional Verification , AMD , System Development Suite , Incisive , in-circuit emulation , Palladium XP , Emulation , in-circuit acceleration , Design Automation Conference , DAC breakfast , System Design and Verification

System, PCB, & Package Design 

What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!

The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call…

• 1 min read
PCB , PCB Layout and routing , bundle compression , interconnects , 2 point flow , global route , Routing , High Speed , Allegro 16.5 , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , disabiling bundle compression , Allegro

Verification

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include…

• 4 min read
AVIP , SystemVerilog , accelerated VIP , Verification IP , uvm , Acceleration , Functional Verification , VIP , Palladium , Palladium XP , Emulation , VIP Catalog , simulation VIP , ACE verification , e language , SCE-MI , SystemC , protocol verification , simulation , verification

Digital Design

Adding Custom Shapes and Text is New and Improved in EDI System 11

You may have noticed that in the Encounter Digital Implementation (EDI) System 11…

• 4 min read
dbGet , add_shape , custom text , custom shapes , add_text , EDI 11.1 , digital implementation , Encounter Digital Implementation , OpenAccess , EDI 11

Verification

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working…

I think all of us engineers have faced at one point or another the need to explain…

• 2 min read
Rapid Protoytping Platform , Virtual System Platform , virtual platforms , awards , Watson , virtual prototypes , American Technology Awards , Jeopardy , System Development Suite , VSP , Incisive , Palladium XP , Raritan , Mother's Day , System Design and Verification , cloud computing , FPGA-based prototyping

Verification

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification
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