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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification

Verification

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage…

Memory management is not something the Specman user is supposed to worry about. Nobody…

• 9 min read
AF , Specman , Memory , garbage , Functional Verification , garbage collection , Specman garbage collection , Incisive , e language , managing memory , Specman data , memory errors , testbench , simulation , memory management , verification

Verification

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal…

This 6 minute video is a quick overview of our formal scoreboard app. Specifically…

• less than a min read
scoreboard , ABV , Joerg Mueller , Formal Analysis , formal , video , formal apps , apps , formal scoreboard , IEV , IFV

System, PCB, & Package Design 

What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements

More high-density interconnect (HDI) improvements including the tuning of the auto…

• 1 min read
PCB , PCB Layout and routing , interconnects , inset vias , Routing , via tangency , Allegro 16.5 , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , PCB design , SPB16.5 , HDI , microvia , Allegro

System, PCB, & Package Design 

Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in A…

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last…

• 1 min read
PCB SI , PCB , SI , DDR2 , transmission line , PCB PI , PDN , Austin , Robert Hanson , "PCB SI" , PCB power integrity , Allegro 16.5 , IBIS-AMI , Power Delivery Network , Signal Integrity , PCB Signal integrity , Allegro PCB SI , PCB design , "PCB PI" , PCI Express , "Power Delivery Network" , DDR3 , Allegro

Verification

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

Digital Design

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Dir…

No matter how you run your power analysis - with Encounter Power System (EPS) or…

• 3 min read
EDI , rail analysis , EPS reports , tutorial , encounter digital implementation system , EPS , encounter , digital implementation , IRdrop , Power Analysis , powergrid view , EM , five-minute , encounter power system , electromigraion

Analog/Custom Design

What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics…

• 2 min read
daa , AMS , Low Power , mixed signal design , mixed signal solution , Mixed-Signal , dac2012 , Mixed signal physical implementation , mixed signal , cortex M , DAC 2012 , ARM , boris murmann , digitally assisted analog , mixed-signal verification

System, PCB, & Package Design 

What's Good About Allegro Via Patterns During Group Routing? See for Yourself in…

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns…

• 3 min read
PCB , PCB Layout and routing , blind vias , diff pairs , inset vias , global route , Routing , staggered vias , layer stacks , Allegro 16.5 , SPB , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , differential pairs , group routing , Differential Pair Support , buried vias , HDI , PCB Capture , Allegro

Verification

My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation…

• 4 min read
AF , IntelliGen , Specman , debug , Functional Verification , Gen debugger , test generation , Gen , Generation , e language , Constraints , constraint not enforced , verification

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML…

• 1 min read
PCB , capture , "capture CIS" , Allegro Design Entry , Design Entry CIS , OrCAD Capture Marketplace , Find command , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , Find result , design , OrCAD , PCB design , Design Entry , SPB16.5 , PCB Capture , Schematic , OrCAD reports

System, PCB, & Package Design 

What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!

The 16.5 release of Allegro Design Workbench ( ADW ) provides support for generic…

• 1 min read
PCB , generic models , Allegro Design Workbench , Library flow , Allegro 16.5 , Library and design data management , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a…

• 8 min read
AF , SystemVerilog , Specman , OVM ML , Functional Verification , Testbench simulation , OVM e , EDA , e , stack trace , Signal Integrity , e language , team specman , Aspect Oriented Programming , eRM , specman crashes , simulation , AOP , IES-XL

Verification

Video: “Drive For Innovation” Finds It At Every Turn

With some notable exceptions, too often technology trade press reporting has been…

• less than a min read
Brian Fuller , Avenet Express , Joe Hupcey III , innovation , "Drive for Innovation" , UBM Electronics , Chevy Volt , EE Times

Verification

Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded…

• 3 min read
zynq , Memory , virtual platforms , TLM , virtual prototypes , SDRAM , Verilog , SystemC memories , SystemC , memory models , modeling memories , linux

Verification

Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV

Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification…

• 2 min read
ABV , CDNLive India , Vinaya Singh , Formal Analysis , NVIDIA , ADS , property-driven simulation , CDNLive! , IEV , Assertion-Driven Simulation , Formal verification , India , Assertion-based verification

Analog/Custom Design

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Ve…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital…

• 3 min read
real number modeling , CDN Live , CDNLive SV 2012 , CDNLive , AMS Designer , LSI , RNM , behavioral models , CDNLive! , wreal , Luo , Virtuoso environment , AMS Verification , mixed-signal verification , verification

Digital Design

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi…

Maximizing the usage of Multi-cut vias by the router is one key to improving yield…

• 2 min read
EDI , EDI system , 28nm , EDI 11.1 , NanoRoute , encounter , via , digital , Digital Implementation , multi-cut via insertion , Brian Wallace , EDI 11 , DFM , "SoC-Encounter"
CDNS - Fix Layout Hompage