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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Making Friends With Parasitic Effects

OK, so the title is perhaps a little optimistic but I'm playing off the saying …

• 2 min read
PAD , Bleasdale , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , Parasitic analysis , Custom IC Design , parasitics

Verification

Corner-Case Conditions Will Get You Every Time

Experienced verification engineers know that most killer bugs lurk deep in the corners…

• 2 min read
Functional Verification , bugs , corner cases , dec , Gordon Bell

Verification

New Interview with Partner Zocalo on Their Assertion Creation Philosophy and Approach…

Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering…

• less than a min read
DAC , ABV , Zocalo , verification strategy , Verification methodology , Functional Verification , formal , assertions , verification

Verification

A SystemC TLM 2.0 ARM Linux Boot Loader

Earlier this year I wrote an article with some details related to loading Linux into…

• 6 min read
TLM2 , virtual platforms , System Design and Verification , TLM 2.0 , embedded software , boot loader , software , SystemC , ARM , linux , System Design and Verification , kernel

System, PCB, & Package Design 

What's Good About Capture Intersheet References? The Secret's in the SPB16.3 Release

The SPB16.3 release of OrCAD Capture now allows you to create intersheet references…

• 5 min read
PCB , SPB16.3 , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , OrCAD , intersheet , Design Entry , Schematic , Allegro

RF Engineering

Measuring Transistor fmax

There were several questions about measuring transistor f max in comments posted…

• 3 min read

Analog/Custom Design

SKILL for the Skilled: Rule of English Translation

An obvious criticism of my previous post SKILL for the Skilled: Making Programs…

• 3 min read
Team SKILL , English translation , Norvig , Lisp , Custom IC Design , SKILL , clarity

Verification

“Everything Assertion Based” -- Assertion-Based Verification (ABV) Comes of Age for…

Preface: are you having trouble (re-)igniting interest in formal, muti-engine, and…

• 5 min read
NextOp , ABV , Zocalo , Functional Verification , Formal Analysis , formal , VIP , PSL , assertion synthesis , metric-driven verification , coverage driven verification (CDV) , assertions , AMBA , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About Mechanical Parts in ADW? Check Out the ADW16.3 Release and See

Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release…

• 2 min read
PCB , SPB16.3 , DEHDL , mechanical parts , SPB 16.3 , Library flow , Library and design data management , PCB Editor , Design Entry HDL , Front-end PCB design , design , Component Information Portal (CIP) , Design Entry , ADW 16.3 , Allegro PCB Editor , ConceptHDL , library , ADW , Allegro

SoC and IP

The 3D SSD

You need three things from a solid-state disk (SSD): speed, capacity, and reliability…

• 1 min read

Verification

Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over…

• 2 min read
High-Level Synthesis , RTL , Hogan , EETimes , SystemC , evolution , HLS , McLellan

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

MDL is an immensely powerful feature in our simulators that allows designers to run…

• less than a min read

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

Measurement Description Language (MDL) is an immensely powerful feature in our simulators…

• less than a min read
analog , Virtuoso , spectreMDL , Spectre , MDL , Custom IC Design

System, PCB, & Package Design 

What's Good About Part Developer and Fonts? You Can Change Them in SPB16.3!

PCB Librarian Expert (sometimes known as Part Developer or PDV ) is the librarian…

• 2 min read
SPB16.3 , part developer , PDV Symbol , Allegro 16.3 , SPB 16.3 , SPB , design , fonts , Design Entry , Librarians , ConceptHDL , library , Allegro

Verification

Does It Get Any Better than CDNLive! India?

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd…

• 3 min read
CDNLive , formal , OVM , ISX , MDV , IFV , techtorial , India , verification

System, PCB, & Package Design 

A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control

This is second in a series of blog posts about making your design cycles shorter…

• 1 min read
PCB , PCB Layout and routing , DDR2 , ECSets , Constraint-driven PCB Design flow , Allegro 16.3 , phase control , XAUI , PCB design , dynamic phase control , DDR3 , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Case Management? SPB16.3 Has a Few New Enhancements!

The SPB16.3 PCB SI release has simplified the use of case management. In previous…

• 1 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , Signal Intregrity , SigXP UI , Allegro 16.3 , SPB 16.3 , SPB , PCB design

Verification

“Formal Design” or “Formal Verification”-- What is the Right Label?

Shortly after DAC 2010, Gabe Morretti wrote a couple of interesting blogs (reference…

• 3 min read
DAC , uvm , ABV , CDNLive , Functional Verification , formal , OVM , EDA360 , EDA , SoC , Silicon Realization , SoC Connectivity , connectivity , IFV

Verification

Broadcom Presentation Shows Value of Transaction-Based Acceleration

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom…

• 1 min read
CDNLive , Acceleration , System Design and Verification , Palladium , broadcom , Emulation , transaction-based , simulation , verification
CDNS - Fix Layout Hompage