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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

The India Circuit

The New India: Rise Of The Cashless Wallets

Can India really ever go cashless? This was one of the topics that was discussed…

• 3 min read
Government of India , cashless economy , digital india , Ezetap , demonetization , make in india

Breakfast Bytes

DAC Monday: Amazon's Things, Handel's Megadesign, Cooley's Troublemakers

Another year, and another DAC. As usual, the proceedings kicked off on Sunday night…

• 14 min read
dac55 , DAC , handel jones , Cooley , ibs , verification

System, PCB, & Package Design 

Improve Your Circuit Manufacturing Yield with Monte Carlo Analysis in PSpice

Generic Spice Technology is past. Let me introduce you to the powerful Monte Carlo…

• less than a min read
RF , OrCAD Capture , PSPICE , PCB design , simulation

Breakfast Bytes

Cadence Cloud

Today Cadence announced Cadence Cloud. This is the beginning of a major change in…

• 7 min read
passport , cloud , cadence cloud , Hosted Design Solutions

Breakfast Bytes

Remember Virtual CAD? DesignSphere Access? What an ASP Was?

Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology…

• 4 min read
asp , cloud , cadence cloud , esd alliance

Verification

Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

Welcome back to our series on cloud verification solutions. This is part two of a…

• 1 min read
uvm , Functional Verification , EDA , HPC , cadence cloud

Verification

App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog…

Welcome back to the third installment of a special multi-part edition of the App…

• 2 min read
SystemVerilog , Tip , Functional Verification , App Note Spotlight

Breakfast Bytes

Automobil Elektronik Kongress 2018

Once a year for 22 years the electronic divisions of the European automotive industry…

• 6 min read
Automotive , ADAS , autonomous vehicles

Breakfast Bytes

What's For Breakfast? Video Preview June 25th to 29th 2018

https://youtu.be/-fwwmFE6yUs Coming from Automotiv Elektronik Kongress (camera…

• less than a min read
dac55 , DAC

Breakfast Bytes

Movie Theater Sound in Your Phone

Dolby Atmos is immersive sound. As Dolby puts it: Dolby transports you into the…

• 3 min read
hifi3 , atmos , Dolby , mwc china , Tensilica , Huawei

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to ADAS  with a Real-Life Example

In this week’s Whiteboard Wednesdays video, Marc Greenberg, walks us through a typical…

• less than a min read
Whiteboard Wednesdays , self-driving car , ISO 26262 , ADAS

Breakfast Bytes

RSA Wrapup: Song, Darling, Thrun

The closing session of the RSA conference was a sort of chat-show hosted by Hugh…

• 5 min read
sebastian thrun , security , artificial intelligence , rsa conference , rsa , kate darling , dawn song

Analog/Custom Design

Virtuoso Video Diary: What's this Net Connected to?

Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where…

• 1 min read
Virtuoso Schematic Editor , Virtuoso , Schematic Editor , Virtuoso Video Diary , Circuit Design , Probes assistant , Custom IC Design , Schematic

Breakfast Bytes

Why Millennial Engineers Should Work for Cadence

Many years ago, when Nokia was at the top of its game—one in every three phones shipped…

• 5 min read
andy kessler , EDA

Academic Network

Academic Track at CDNLive EMEA 2018

From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days…

• 6 min read
hololens , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Risc V , Academic Network , UC Berkeley

Verification

Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

Welcome to the first installment of a three-part blog series examining the issues…

• 2 min read
cloud-based verification , Functional Verification , cadence cloud , cloud computing

Breakfast Bytes

The Design Infrastructure Alley

One of the new things at DAC this year is the Design Infrastructure Alley. The Alley…

• 4 min read
dac55 , DAC , infrastructure alley

Breakfast Bytes

Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet…

• 3 min read
DAC , ChipEstimate.com , Perspec , pss

System, PCB, & Package Design 

What Is COM /JCOM Channel Compliance All About?

In today’s world of double-digit gigabit-per-second data rates it is imperative that…

• 3 min read
SI , JCOM , Channel Operating Margin (COM) , COM/JCOM , JCOM channel compliance , COM , Channel Operating Margin , Signal Integrity , SystemSI
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