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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

RF Engineering

Measuring Transistor fmax

There were several questions about measuring transistor f max in comments posted…

• 3 min read

Analog/Custom Design

SKILL for the Skilled: Rule of English Translation

An obvious criticism of my previous post SKILL for the Skilled: Making Programs…

• 3 min read
Team SKILL , English translation , Norvig , Lisp , Custom IC Design , SKILL , clarity

Verification

“Everything Assertion Based” -- Assertion-Based Verification (ABV) Comes of Age for…

Preface: are you having trouble (re-)igniting interest in formal, muti-engine, and…

• 5 min read
NextOp , ABV , Zocalo , Functional Verification , Formal Analysis , formal , VIP , PSL , assertion synthesis , metric-driven verification , coverage driven verification (CDV) , assertions , AMBA , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About Mechanical Parts in ADW? Check Out the ADW16.3 Release and See

Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release…

• 2 min read
PCB , SPB16.3 , DEHDL , mechanical parts , SPB 16.3 , Library flow , Library and design data management , PCB Editor , Design Entry HDL , Front-end PCB design , design , Component Information Portal (CIP) , Design Entry , ADW 16.3 , Allegro PCB Editor , ConceptHDL , library , ADW , Allegro

SoC and IP

The 3D SSD

You need three things from a solid-state disk (SSD): speed, capacity, and reliability…

• 1 min read

Verification

Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over…

• 2 min read
High-Level Synthesis , RTL , Hogan , EETimes , SystemC , evolution , HLS , McLellan

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

MDL is an immensely powerful feature in our simulators that allows designers to run…

• less than a min read

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

Measurement Description Language (MDL) is an immensely powerful feature in our simulators…

• less than a min read
analog , Virtuoso , spectreMDL , Spectre , MDL , Custom IC Design

System, PCB, & Package Design 

What's Good About Part Developer and Fonts? You Can Change Them in SPB16.3!

PCB Librarian Expert (sometimes known as Part Developer or PDV ) is the librarian…

• 2 min read
SPB16.3 , part developer , PDV Symbol , Allegro 16.3 , SPB 16.3 , SPB , design , fonts , Design Entry , Librarians , ConceptHDL , library , Allegro

Verification

Does It Get Any Better than CDNLive! India?

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd…

• 3 min read
CDNLive , formal , OVM , ISX , MDV , IFV , techtorial , India , verification

System, PCB, & Package Design 

A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control

This is second in a series of blog posts about making your design cycles shorter…

• 1 min read
PCB , PCB Layout and routing , DDR2 , ECSets , Constraint-driven PCB Design flow , Allegro 16.3 , phase control , XAUI , PCB design , dynamic phase control , DDR3 , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Case Management? SPB16.3 Has a Few New Enhancements!

The SPB16.3 PCB SI release has simplified the use of case management. In previous…

• 1 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , Signal Intregrity , SigXP UI , Allegro 16.3 , SPB 16.3 , SPB , PCB design

Verification

“Formal Design” or “Formal Verification”-- What is the Right Label?

Shortly after DAC 2010, Gabe Morretti wrote a couple of interesting blogs (reference…

• 3 min read
DAC , uvm , ABV , CDNLive , Functional Verification , formal , OVM , EDA360 , EDA , SoC , Silicon Realization , SoC Connectivity , connectivity , IFV

Verification

Broadcom Presentation Shows Value of Transaction-Based Acceleration

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom…

• 1 min read
CDNLive , Acceleration , System Design and Verification , Palladium , broadcom , Emulation , transaction-based , simulation , verification

RF Engineering

New Fast Envelope in MMSIM10.1 is *Really* Fast and Accurate!

Traditionally, envelope analysis is used to simulate circuits with modulated inputs…

• 1 min read
RF , envelope , MMSIM , fast envelope , simulation

Verification

Open Mobile Summit -- What‘s Happening in the World of Applications

I attended last week's Open Mobile Summit in San Francisco last week. This is a twice…

• 4 min read
Open Mobile Summit , applications , android , EDA360 , google , apps , superphones , smartphones

System, PCB, & Package Design 

What's Good About Allegro GRE Planning? You’ll Need the SPB16.3 Release to See!

This new SPB16.3 Global Route Environment (GRE) Plan Status and Router Status functionality…

• 2 min read
PCB , PCB Layout and routing , SPB16.3 , global route , Routing , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , GRE , Predictable PCB design , Allegro

Verification

System Bring-Up - THE Critical Path in the System Development Process

The electronic industry is moving from hardware-defined products to software-defined…

• 2 min read
prototyping , Bring-up , Acceleration , debug , system realization , Palladium , Emulation , bringup , System Design and Verification , verification

Verification

2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman…

If you are running short on time and can't view all the videos of the 2010 CDNLive…

• less than a min read
SystemVerilog , Cadence Connections , NextOp , AMS , uvm , Specman , ABV , Zocalo , verification strategy , CDNLive , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Mixed Signal Verification , e , SoC , SVA , ISX (Incisive Software Extensions) , Silicon Realization , AMIQ , assertion synthesis , Aspect Oriented Programming , ISX , MDV , IEV , IFV , AOP
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