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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—Key Metrics for Embedded Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , embedded neural networks

System, PCB, & Package Design 

What's Good About the Altium to Allegro PCB Editor Translator? It’s Now Available…

The current 16.6 HotFix now provides support for the Altium to Allegro PCB Editor…

• 2 min read
PCB , Allegro 16.6 , DEHDL , SPB , Design Entry HDL , PCB design , Grzenia , Allegro PCB Editor , Allegro

Breakfast Bytes

Misfit Shine 2 Lasts for 6 Months on a Coin Cell. How Do They Do That?

You can't go for very long without hearing about the Internet of Things (IoT) in…

• 3 min read
ClariTek , IoT , Misfit , Shine 2 , Breakfast Bytes , Patrick Mannion

Breakfast Bytes

IEDM Examines Options for 5nm...Academics and Industry Examine the Options

At IEDM in December, there was a full-day course looking at the options for transistors…

• 3 min read
transistors , interconnect , feol , carbon nanotube , optical interconnect , FinFET , beol , IEDM , Breakfast Bytes , devices

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Differential Pair Return Path Vias? Significant…

The Allegro PCB Editor 16.6-2015 release (requires login) now provides support for…

• 7 min read
PCB Layout and routing , diff pairs , Allegro 16.6 , SPB , differential pair , PCB design and layout , Grzenia , Allegro PCB Editor , differential pairs , return path vias

Academic Network

Genus Synthesis Solution 15.2 Now Available to Academia

To support academia using the latest industry-standard tools, Cadence's Genus Synthesis…

• 1 min read
Genus , Cadence Academic Network , academia

Verification

Using Tables to Handle Configurability in Incisive Enterprise Specman

Most, if not all, designs which are being verified today are configurable. This is…

• 2 min read
IntelliGen , configurable designs , Specman , tech tips , Funcional Verification , Incisive Enterprise Specman

Breakfast Bytes

Designing USB 3.1? You Need Sigrity 2016

The most important new connector in town (especially if that town was Las Vegas during…

• 4 min read
USB 3.0 , USB Power Delivery , USB Type-C , usb 3.1 gen 1 , usb 3.1 gen 2 , sigrity 2016 , USB , ibis-ami model , Sigrity , USB 3.1 , ces2016 , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—SSD Controllers with Tensilica Processors

In this week's Whiteboard Wednesdays video, Neil Robinson follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Neil Robinson , Tensilica , SSD controllers

Breakfast Bytes

Embedded Neural Network Summit—How to Build a Silicon Brain

On February 9, Cadence is hosting an all-day Embedded Neural Network Summit., with…

• 2 min read
deep learning , enns , Tensilica , convolutional neural networks , embedded neural networks , Breakfast Bytes

SoC and IP

New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivit…

PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface…

• 1 min read
PCIe Gen4 , pcie4 , 16Gbps PHY IP , SerDes , SerDes IP

Breakfast Bytes

16Gbps SerDes Multiprotocol Multilink PHY IP

In any advanced node, one of the most important pieces of IP is a high-performance…

• 4 min read
USB 3.0 , pcie4 , 10G-KR , USB , pcie3 , pcie2 , PCIe , 16 Gbps , SerDes , USB 3.1 , SATA , sata3 , Breakfast Bytes

System, PCB, & Package Design 

Customize the Organization of Bond Wires in Your Artwork Films with SiP Layout and…

When it comes to IC Package substrates, Gerber is still one of the most common, most…

• 4 min read
SiP , Allegro package design , Digital SiP design , IC package design , APD , package design , manufacturing , wirebonding , substrate design tools

Breakfast Bytes

Mobile Unleashed: a New Book About ARM

Mobile Unleashed is subtitled The Origin and Evolution of ARM Processors in Our Devices…

• 3 min read
mobile unleashed , mobile , ARM , arm history , Breakfast Bytes

Breakfast Bytes

What Happens in Vegas...May Be in Your Next Chip

Cadence was at CES last week showing the most recent additions to their vision, audio…

• 2 min read
USB Type-C , Consumer Electronics Show , CES , CES 2016 , Tensilica , HiFi DSP , audio weaver , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—SSD Controller Basics and Trends

In this week's Whiteboard Wednesdays video, Neil Robinson talks about SSD controllers…

• less than a min read
Whiteboard Wednesdays , IP , Neil Robinson , Tensilica , SSD controllers

Breakfast Bytes

Cars, Drones, 8K, and VR/AR—Consumer Electronics Show 2016

CES is held in January each year. It is the largest conference in Las Vegas, which…

• 6 min read
USB Type-C , Consumer Electronics Show , CES 2016 , las vegas , virtual reality , drones , Tensilica IP , autonomous vehicles , augmented reality , Breakfast Bytes

SoC and IP

The Future of High-Speed SerDes

David Axelrad, product marketing manager, SerDes IP, presents Cadence's position…

• less than a min read
PCIe Gen4 , pcie4 , SerDes , gsa

Breakfast Bytes

Tempus Has Over 200 Tapeouts Within 2 Years of Rollout

One of the challenges with any new tool is to drive adoption. There really is a …

• 3 min read
PBA , Tempus , adoption , path-based analysis , tapeout
CDNS - Fix Layout Hompage