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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Latest blogs

Analog/Custom Design

Virtuoso IC6.1.7 ISR21 and ICADV12.3 ISR21 Now Available

The IC6.1.7 ISR21 and ICADV12.3 ISR21 production releases are now available for download…

• 2 min read

Whiteboard Wednesdays

Whiteboard Wednesday - Tensilica Hardware Safety Kit ISO 26262

In this week's Whiteboard Wednesday video, Divya Kalimuthu highlights all of the…

• less than a min read
Whiteboard Wednesdays , functional safety , ISO 26262

Breakfast Bytes

DAC: Straight Talk with Lip-Bu Tan

For the last few DACs, every lunchtime the DAC Pavilion has an interview by Ed Sperling…

• 7 min read
Ed Sperling , Automotive , 3nm , Lip-Bu Tan , 55DAC , 5nm , 7nm , Design Automation Conference

Digital Design

A Decade of Building CODECs with High-Level Synthesis

Over the past decade, we have seen a dramatic increase in the size of common video…

• 6 min read
High-Level Synthesis , Stratus , SystemC , HLS

Breakfast Bytes

ESD Alliance Workshop on Digital Marketing

I gave a teaser introduction to the Digital Marketing Workshop that the ESD Alliance…

• 4 min read
digital marketing , onespin , esd alliance

Analog/Custom Design

Virtuosity: A Guide to Bindkeys for Interactive and Assisted Routing Commands

I'm sure you are well-versed with the benefits of using bindkeys. So, to have a better…

• 2 min read
Interactive Routing , Create Wire , custom/analog , Virtuoso Space-based Router , VSR , Routing , Create Stranded Wire , Interactive and Assisted Routing , Wire Editing , Mixed-Signal , Layout , Virtuoso , Virtuosity , mixed signal , createbus , Custom IC Design , Assisted Routing , Virtuoso Layout Suite , Custom IC , Interactive Wire Editing

Breakfast Bytes

Liberate Trio: Characterization Suite in the Cloud

Years ago, library characterization used to be fairly straightforward. The library…

• 3 min read
characterization , liberate trio , cloud , cadence cloud , ARM

Breakfast Bytes

Overcoming Bias in Computer Vision

At the recent Embedded Vision Summit, Will Byrne gave a presentation Overcoming Bias…

• 6 min read
stereotype , embedded vision , bias

The India Circuit

Thirty Years As One Team

Last week, Cadence was recognized as No 28 in the “Best Companies to Work For” study…

• 3 min read
Great Place To Work Institute , GPTW , Cadence India , Best Companies to Work For

Breakfast Bytes

Want to Go on a Second Date?

Yesterday I told you about the Doomsday algorithm in my post Doomsday in 1900 Was…

• 6 min read
offtopic , DATE , microsoft

Breakfast Bytes

Doomsday in 1900 Was a Wednesday

Cadence is off today, so time for an off-topic post. In my post Short Papers last…

• 6 min read
offtopic , DATE , john conway

SoC and IP

Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband…

• 1 min read
DSP , IoT , Fusion , ip cores , Tensilica , nb-iot

Breakfast Bytes

What's For Breakfast? Video Preview July 9th to 13th 2018

https://youtu.be/d04TXTJKx5o Coming from Cadence EBC (camera Lan Ly) Monday: ESD…

• less than a min read
semicon , imec , 55DAC , esd alliance , palladium cloud

Breakfast Bytes

/* You Are Not Expected to Understand This */

The title of this post, you are not expected to understand this, is one of the most…

• 7 min read
ken thompson , unix , bug , john lyons , dennis ritchie

Breakfast Bytes

A History of PSS

In a remark attributed to Otto von Bismarck (or perhaps misattributed), it is said…

• 6 min read
Perspec , pss , portable stimulus standard , verification

Verification

Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

Welcome back to our series on cloud verification solutions. This is the final part…

• 2 min read
security , Functional Verification , cadence cloud , xcelium , palladium cloud

Verification

UVM-ML- Managers’ Freedom of Choice

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is…

• 5 min read
Specman , Specman/e , UVM-ML , Specman e , UVM multi-language , UVM-e , UVM ML , multi-language , multi-language UVM , multi-language verification , verification

Breakfast Bytes

DAC Wednesday: Denali, Patterson on Architecture, Rowen on Deep Learning, Analog…

Tuesday evening finished with the Denali Party. Since it's 8 years since Cadence…

• 13 min read
Analog artist , analog , isa , reliability

Breakfast Bytes

What's For Breakfast? Video Preview July 2nd to 6th 2018

https://youtu.be/QoFQImb0xk4 Coming from DAC (camera Sean) Monday: /* You are…

• less than a min read
liberate trio , doomsday , john conway , embedded vision , cloud , cadence cloud
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