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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Digital Design

Coming This Friday January 9th: Encounter Digital Implementation Office Hours

Happy New Year everyone! I hope you all had a restful, enjoyable and healthy holiday…

• 1 min read
Digital Implementation forums , chat , Encounter Digital Implementation

Verification

Power tool: The Reflection API

One endless source of neat little tricks is the Reflection API built into Specman…

• 1 min read

Verification

Metric-Driven Verification in a Box...

In my last few posts, I was explaining our focus here in Cadence Verification on…

• 1 min read
metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Cadence VIP portfolio , OVM , VIP , Coverage-Driven Verification , CDV , e , Verification IP modeling , eRM

Verification

Make Your Command Line Life Easier With "specman -e"

Hi All, It always amazes me to see just how many Specman users make use of the interactive…

• 1 min read
Specman , Incisive Enterprise Simulator (IES) , IES

Verification

Who said Cadence Can't Invent New Technology Anymore?

I and the rest of the Cadence C-to-Silicon Compiler (CtoS) team were thrilled yesterday…

• 1 min read
deepchip , System Design and Verification , C-to-Silicon

Verification

Shout-out: Q1 2009 DV Club Schedule Posted

Last month I had the pleasure of attending a DV Club lunch presentation on analog…

• less than a min read
events , verification strategy , Verification methodology , Functional Verification

Verification

Thanks for a Great 2008!

Even though 2008 will probably go down in history as the year of Doom and Gloom we…

• 1 min read

Digital Design

It’s the Season of Giving – Send Me Your Design Innovations!

In the last blog, I wrote about innovating your way out of recession with new designs…

• 2 min read
digital Implementationg , innovation , encounter

Verification

Using e Ports

The other day I saw some posts to the Yahoo Specman group regarding e ports. The…

• 3 min read
IEEE 1647 , Specman , verification strategy , Verification methodology , Testbench simulation , e , Verification IP modeling , eRM , Incisive Enterprise Simulator (IES) , IES

Verification

Quickly Create and Manage e Functional Coverage

As a verification engineer, I have always found creating coverage code to be one…

• 3 min read
IEEE 1647 , Specman , Verification methodology , metric driven verification (MDV) , Functional Verification , MDV techtorial , Coverage-Driven Verification , CDV , e , Enterprise Manager , Enterprise Planner , coverage driven verification (CDV)

System, PCB, & Package Design 

Thank You!

As the 2008 year comes to a close, I wanted to say Thank You! Thanks to the hard…

• 1 min read
PCB design

Verification

Video Demo: “irun” – The Way to run Simulations!

The irun utility provides a use-model to run simulations with Incisive Simulator…

• less than a min read
Functional Verification , Incisive Enterprise Simulator (IES)

System, PCB, & Package Design 

What's Good About the SPB16.2 PSpice Models? BSIM4 Support!

The SPB16.2 release now has new MOSFET device Model BSIM4 Support in PSpice PSpice…

• 4 min read
RF , SPB 16.2 , PCB design , BSIM4 , MOSFET

Verification

Is it Necessary to Improve the Quality of Consumer Electronics?

Fellow blogger Joe Hupcey passed along a link covering the recent launch of the BlackBerry…

• 4 min read
System Design and Verification , software acceleration , blackberry , Enterprise Manager , ISX

Verification

Constraint Layering - Fine Tuning Your Environment - Part 2

In my last post , I talked briefly about constraint layering in which I gave an extremely…

• 4 min read
IEEE 1647 , Specman , verification strategy , Verification methodology , Functional Verification , Testbench simulation , e , Aspect Oriented Programming , IES , AOP

Analog/Custom Design

Video Chat with Lead Architect of Virtuoso Accelerated Parallel Simulator

Virtuoso Accelerated Parallel Simulator was just released and I asked Ilya Yusim…

• 1 min read
mixed-signal simulators , MMSIM , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Become an Encounter Digital Implementation System Specialist and Win Cool Prizes

Last week, we announced the Encounter Digital Implementation System along with a…

• less than a min read

Verification

New Technical Blog on e & Specman Technology

Specmaniacs of the world: rejoice! Members of Team Specman have just launched their…

• less than a min read
IEEE 1647 , Specman , e

Verification

Constraint layering - Fine Tuning Your Environment - Part 1

In today's environment of ever growing complexity and ever shrinking schedules,…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , verification strategy , Verification methodology , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP
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