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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over…

• 3 min read
PCB , PCB Layout and routing , RF , Allegro 16.6 , RF PCB , Routing , 16.6 routing , PCB Editor , Layout , design , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Digital Design

SPICE Correlation Made Easy by Encounter Timing System (ETS)

Hello, and welcome to my first blog! As an application engineer in customer support…

• 4 min read
app note , Static timing analysis , ets , mukesh , STA , spice correlation , Spectre , signoff , ETS create_spice_deck , Encounter Timing System , SPICE

Verification

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews

System, PCB, & Package Design 

Leverage System Planning to Maximize Performance of Silicon Interposer

Recently, an article was published in Chip Scale Review by Cadence product manager…

• 2 min read
SI , PI , Chip Scale Review , SiP , IC Packaging , Team Allegro , 3D IC , Kevin Rinebold , 3D-IC , Power Integrity , TSV , silicon interposer , Signal Integrity , 2.5D IC , system planning , system co-analysis , 2.5D

System, PCB, & Package Design 

What's Good About RF SiP and Data Management? Look to 16.6 and See!

The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity…

• 2 min read
PCB , IC Packaging and SiP Design , Allegro RF SiP , SiP , IC Packaging , Allegro 16.6 , die abstracts , RF SiP , IC/package co-design , design , PCB design , Grzenia , SiP Layout , die abstract , Virtuoso SiP

System, PCB, & Package Design 

Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application…

Whether it is reducing mouse clicks, minimizing access to menus, eliminating the…

• 3 min read
package , SiP , IC Package , IC Packaging , cadence , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , Allegro Package Designer , APD 16.6 , SiP Layout , wirebonding

Analog/Custom Design

Mixed-Signal Technology Summit in Japan Provides Technology Updates

Japan’s semiconductor industry is undergoing a significant change in recent years…

• 3 min read
AMS , uvm , Virtuoso-AMS , microcontrollers , ARM Cortex M0 , mixed signal design , Mixed-Signal On Top , AMS-Designer , MS ToT , IC 6.1 , A/MS , mixed signal methodology , tech on tour , AMS Designer , analog on top , Open Access , Cortex-M , Verilog-AMS , analog , Mixed-Signal , encounter , Mixed-Signal Technology Summit , LDE , analog behavioral models , analog/mixed-signal , Virtuoso , mixed-signal book , Cortex-M0 , oa , ClioSoft , metric-driven verification , mixed signal , wreal , micro-controllers , ARM , ARM-Cortex-M , OpenAccess , Common Power Format , AMS Verification , TowerJazz , Matlab , real number

Verification

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to T…

One of the main benefits of moving the design entry point up in abstraction from…

• 1 min read
uvm , TLM , Jack Erickson , Functional Verification , abstraction , webinar , metric-driven verification , SystemC , Watanabe , MDV , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI Setup/Audit? 16.6 has Many New Enhancements!

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release…

• 8 min read
PCB SI , PCB , SI , diff pairs , Allegro 16.6 , setup/audit , Signal Intregrity , SigXP UI , DRC , 16.6 , PCB Signal and power integrity , "PCB SI" , High Speed , PCB power integrity , diff pair , setup , differential pair , Signal Integrity , audit , design , Allegro PCB SI , PCB design , "PCB PI" , Grzenia , differential pairs , SI analysis and modeling , Differential Pair Support , power , Allegro

System, PCB, & Package Design 

Open Cavity Design Tools for IC Packaging Now Available in 16.6

In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete…

• 3 min read
IC Package , IC Packaging , packaging , open cavity , 16.6 , IC Packaging and SiP , Allegro Package Designer , Sigrity , APD 16.6 , SiP Layout , cavity

Verification

New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion…

• 1 min read
ACE , ABV , Joerg Mueller , ABVIP , Mirit Fromovich , ACE verification , ARM , AMBA4

Analog/Custom Design

SKILL for the Skilled: Part 5, Many Ways to Sum a List

In the most recent posts of SKILL for the Skilled (see previous post here ) we looked…

• 5 min read
Team SKILL , Jim Newton , summing , Virtuoso , Lisp , SKILL++ , sumlist , SKILL

Verification

Techniques to Boost Incisive Simulation Performance

Functional verification is the biggest challenge in delivering more complex electronic…

• 3 min read
performance , Accleration , simulation speed , Incisive Enterprise Simulator (IES)

Verification

UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented…

• 1 min read
AF , uvm , Specman , Functional Verification , vr_ad , Register Package , e language , UVMe , register enhancements

Verification

Optimizing ARM Based Designs for Low Power using Emulation

The month November goes to the Brits, no question. Not only did the James Bond movie…

• 5 min read
ESL Market , Nufront , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Peng Wang , cadence , Acceleration , Functional Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Palladium XP , Emulation , ARM , Schirrmeister , low power optimization

RF Engineering

MMSIM 12.1 SpectreRF -- Preview of Coming nport Attractions! Part 2

Greetings, MMSIM 12.1 contains many new features to aid RF designers. Many of these…

• 2 min read
nport , RF , RF Simulation , analog/RF , Circuit simulation , Wilsey , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , nport settings , Virtuoso Spectre Simulator GXL , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , harmonic balance , simulation

Verification

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are…

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying…

• less than a min read
IEEE 1647 , Specman , Hannes Froehlich , Functional Verification , MOOC , Udacity , training , VA Partners , verification alliance , e language

Digital Design

The Case for the Tiny Testcase

I often joke with customers that, although I realize they have to work on large designs…

• 2 min read
debug , tiny testcase , testcase , Test , encounter , Digital Implementation , small testcase , test case , Bob Dwyer , verification
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