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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About Cadence PCB Design and SI/PI Analysis Products? The 16.6 release…

I’m taking a brief detour from the usual product technical details this week to mention…

• 2 min read
PCB , IC Packaging and SiP Design , Cadence Design Systems , SiP , Allegro 16.6 , Design Entry CIS , DEHDL , FPGA System Planner , High Speed , Allegro Design Workbench , PSPICE , SPB , PCB Editor , High-Density Interconnect , Constraint Manager , Design Entry HDL , Layout , OrCAD , PCB design , AMS simulation , Grzenia , Allegro PCB Editor , ConceptHDL , Allegro

Breakfast Bytes

Is it Hot? Ask Joules

Ever since Pat Gelsinger, then CTO of Intel, shocked everyone with his power graphs…

• 5 min read
Low Power , RTL , Joules , power , Breakfast Bytes , joules rtl power solution

Breakfast Bytes

The Consolidator Makes a Rare Public Appearance: Hock Tan's Top Ten List

On Saturday I attended the Chinese American Semiconductor Professional Association…

• 5 min read
forecast , Avago , consolidator , broadcom , hock tan , caspa , consolidation , lsi logic

Whiteboard Wednesdays

Whiteboard Wednesdays—MIPI Protocol Trends

In this week's Whiteboard Wednesdays video, Moshik Rubin takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , IP , MIPI , MIPI protocols

Breakfast Bytes

IEEE Computer Society: Automotive Cybersecurity

On the third Thursday of each month the IEEE Computer Society of Silicon Valley has…

• 5 min read
security , Automotive , IEEE , Breakfast Bytes

Breakfast Bytes

Emulation: the Key to Virtual Platforms

Between about 2000 and 2010, there were a number of startup companies that attempted…

• 5 min read
virtual platforms , RTL , Palladium , Emulation

Breakfast Bytes

Weekly News—October 23rd 2015

ARM Acquires Carbon ARM announced that it had acquired Carbon Design Systems.…

• 3 min read
Western Digital , SanDisk , IoT , KLA-Tencor , Lam Research , ARM , semiconductors

Life at Cadence

Cadence Is the #21 World’s Best Workplace!

We are honored to be named #21 on FORTUNE’s list of the Best Global Companies to…

• 1 min read
World's Best , Culture , Community , innovation , cadence , Fortune , GPTW , Fortune 100 best companies to work for , great place to work

Breakfast Bytes

Lawyers, Guns, and Money: An Evening with EDAC on Patents

Next Thursday, October 29, 2015, the Electronic Design Automation Consortium (EDAC…

• 5 min read
VLSI , US Patent and Trademark Office , USPTOSV , EDAC , patents , patent litigation , Breakfast Bytes

Analog/Custom Design

Virtuosity: Things I Learned in June and July 2015 by Browsing Cadence Online Su…

Cadence Online Support Release Highlights July 2015 Some nice enhancements to…

• 7 min read
Analog Design Environment , ADE XL , Spectre , PVS , Custom IC Design , ICRP , Virtuoso Layout Suite XL

Breakfast Bytes

How Is Google So Good at Recognizing Cats?

Convolutional Neural Networks (CNNs) are a key technique for image recognition. As…

• 3 min read
performance , Low Power , Tensilica , convolutional neural nets , neural networks , CNN , power , neural nets , image recognition , Breakfast Bytes

Analog/Custom Design

Virtuosity: Things I Learned in August and September 2015 by Browsing Cadence Online…

Cadence Online Support Features Setting the Release Preferences for your search…

• 5 min read
AMS , ADE , spectreRF , Liberate , PVS , Custom IC Design , XLME

Digital Design

Performance, Power, Area. It's All You Need to Know—or Is It?

Whether it's in a technical paper, a pundit's article, or a live discussion with…

• 2 min read
High-Level Synthesis , PPA , Stratus , SystemC , HLS

SoC and IP

Lowering Energy Consumption in Always-on IoT Designs

As a lead design engineer on the Tensilica R&D team, Dr. Avinash Lingamneni certainly…

• 5 min read
Low Power , always on , IoT , wearable , Tensilica , mobile

Breakfast Bytes

I've Got My Personal Portable Communications Equipment. But Where's My Hoverboard…

You have probably seen the Back to the Future trilogy. In Back to the Future II Marty…

• 3 min read
electronics , moore's law , hoverboard , Marty McFly , Back to the Future

Whiteboard Wednesdays

Whiteboard Wednesdays—Cadence IP Solution for USB Type-C

In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the components…

• less than a min read
DSP , Whiteboard Wednesdays , IP , DisplayPort , USB , Tensilica , Xtensa , Type-C , multi-protocol

Verification

MIPI CSI-2—What's Cooking with the Most Popular Mobile Camera Interface?

The MIPI CSI-2 (Camera Serial Interface) specification is celebrating its tenth birthday…

• 2 min read
Verification IP , MIPI Alliance , IoT , VIP , MIPI , CSI

Breakfast Bytes

One Connector to Rule Them All: USB Type-C

The original USB connector seems to be the only connector where it is always the…

• 5 min read
USB Type-C , DisplayPort , USB , IP subsystem

Breakfast Bytes

IEEE Elects EDA Professional as President

When I lived in England, newspapers had a tradition of not mentioning other newspapers…

• 4 min read
Karen Bartleson , EDA standards , Electronic design , IEEE
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