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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Verification

Teradyne "Formally" Adopts JasperGold FPV

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation…

• 2 min read
Teradyne , FPV , CDNLive , customer success , JasperGold , Formal verification

Analog/Custom Design

Virtuosity: Can I Speed up My Plots?

If your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® ADE XL setup…

• 3 min read
Analog Design Environment , ADE GXL , ADE Explorer , Explorer , ADE XL , analog , license , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuosity , mixed signal , Custom IC Design , ADE Assembler

Breakfast Bytes

Rowen on Vision, Innovation, and the Deep Learning Explosion

The keynote for the second day of the Linley Processor Conference was by Chris Rowen…

• 5 min read
Chris Rowen , deep learning , linley processor conference , deeplearningmachinelearning , Computer Vision , Tensilica , vision , neural networks , Breakfast Bytes

Verification

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AM…

It’s been quite a long 5-year journey building and deploying Performance Analysis…

• 2 min read
iwb , interconnect , amba5 , Interconnect Workbench , Palladium , Performance Analysis , AMBA , CoreLink , xcelium , ARM

Computational Fluid Dynamics

Aerodynamic Simulation of a NASA Common Research Model (CRM) Aircraft for JAXA APC…

Born through the merger of three previously independent organizations on October…

• 5 min read

Breakfast Bytes

Linley Gwennap on the Microprocessor Market

Linley Gewennap always gives the opening keynote for the Linley Microprocessor Conference…

• 6 min read
Automotive , Intel , risc-v , linley processor conference , deeplearningmachinelearning , processor , AMD , linley group , IoT , Tensilica , Internet of Things , ADAS , ARM , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview October 16th to 20th 2017

https://youtu.be/CUabZn_-1_M Coming from a cartoon world (camera Sean) Monday…

• less than a min read
metric driven signoff , Metric Driven Verification , AMD , semi , vishal kapoor , sjsu , Jim Hogan , strategic materials conference , Oski , Formal verification

Breakfast Bytes

The Rise of the China IC Industry

At the SEMI Strategic Materials Conference, SMC, Lung Chu, who heads up SEMI China…

• 5 min read
IC , SEMI China , China , semicon china , Lung Chu , SEMI Strategic Materials Conference , smc , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Automotive Memory Trends and Technologies

In this week's Whiteboard Wednesdays, the first in a three-part series, Scott Jacobson…

• less than a min read
Automotive , Whiteboard Wednesdays , NAND flash , automotive electronics , memory models

Breakfast Bytes

Grace Hopper Celebration of Women in Computing

Last week was the Grace Hopper Celebration of Women in Computing (GHC), held in Orlando…

• 6 min read
women in computing , grace hopper , telle whitney , anita borg institute , Breakfast Bytes

Learning and Support

Shorten Your Time to Market! Get Started with Training Bytes

How can you become an expert in your field? Access our short self-help videos called…

• less than a min read
videos , Self Learning , Support , training bytes

Breakfast Bytes

Logical Equivalence Checking to Get Smart

In the late 1960s and early 1970s, there was a TV show called "Get Smart." It was…

• 5 min read
conformal lec , cdnlive korea , logical equivalence checking , LEC , conformal smart lec , Breakfast Bytes

Breakfast Bytes

Computational Origami

At the recent Decoding Formal Club meeting, organized by Oski and sponsored by Cadence…

• 4 min read
computational origami , robert lang , origami , Breakfast Bytes , Formal verification

Digital Design

Faster and Smarter

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about…

• 1 min read
cdnlive korea , deep learning , CDNLive , machine learning , digital , signoff

Analog/Custom Design

Virtuosity: Power Filtering!

Finally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data…

• 2 min read
Analog Design Environment , ADE Explorer , Filtering , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ADE Assembler

Breakfast Bytes

EDPS: The Remains of the Day

EDPS is the Electronic Design Process Symposium, historically held in Monterey, but…

• 12 min read
deep learning , electronic design process symposium , EDPS , Test , machine learning , design , Breakfast Bytes

System, PCB, & Package Design 

CDNLive China: Interviewing with Allegro R&D VP Saugat Sen

Recently, CDNLive China was held in Shanghai. What are the highlights of PCB Track…

• 2 min read
CDNLive , cdnlive china , PCB design , Allegro

Breakfast Bytes

CDNLive Taiwan Automotive Panel

At CDNLive in Taiwan in August, there was a record number of attendees, with about…

• 8 min read
Automotive , hsinchu , CDNLive , TSMC , Renesas , cdnlive taiwan , phison , ADAS , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, discusses…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks , CNN
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