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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

The 40th Anniversary of LAMBDA Magazine

Forty years ago today, January 8, 1980, the first issue of LAMBDA magazine was published…

• 8 min read
vlsi technology , lambda magazine , mead and conway

System, PCB, & Package Design 

IC Packagers: Four Reasons to Avoid Multi-Layer Flip-Chip Pin Padstacks

Designing a package substrate, there are things that many of us do that perhaps we…

• 5 min read
Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: PCB Electronics—Six Tasks to Prepare Board for Manufacturing

You have placed components and routed the board. You are finally ready to send the…

• 5 min read
PCB Editor

Breakfast Bytes

Open Source in 2020

I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source…

• 9 min read
open source eda , open source

Breakfast Bytes

Protium and Palladium 1st=

We just finished 2019, of course, so it is time for annual "Best of 2019" lists.…

• 5 min read
Protium , Palladium , embedded software , Emulation

Breakfast Bytes

The History of Lithography, Part 2: From Double-Patterning to EUV

This is a continuation of yesterday's post The History of Lithography, Part 1: From…

• 8 min read
asml , lithography , Double Patterning , multi-patterning , EUV

Breakfast Bytes

The History of Lithography, Part 1: From Stones to Lasers

Lithography was originally a way of printing using a flat stone. Lithos (or λίθος…

• 7 min read
lithography , 193i , RET

The India Circuit

2019: The Year That Was...And Some Surprising News

The biggest happening in 2019 for India was, of course, the general elections. (Though…

• 3 min read
5G , artificial intelligence , deep learning , 2019 , Deep Tech , AI

System, PCB, & Package Design 

The Year That Was: PCB Design Blogs in 2019

The first series BoardSurfers is about PCB designing. It provides information on…

• 2 min read
Library and design data management , PCB Editor , 17.4-2019 , PCB design

System, PCB, & Package Design 

IC Packagers: Stepping into 2020

We started 2019 with the promise to cover all the topics that might interest you…

• 2 min read
Allegro Package Designer

System, PCB, & Package Design 

IC Packagers: Routing Clean-Up Prior to Manufacturing

A fantastic year is ending, so I want to take a quick opportunity to go over some…

• 5 min read
Allegro Package Designer

System, PCB, & Package Design 

IC Packagers: Guiding Your Team with Workflows

The flow for efficiently and correctly designing a package substrate layout is a…

• 5 min read
APD

Breakfast Bytes

Sunday Brunch Video for 22nd December 2019

https://youtu.be/iEuzyt_6O_A Made in my living room (camera Carey Guo) Monday: The…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

如何利用Allegro SiP Layout工具5步实现复杂引线框架封装的完整设计？

文章翻译自Cadence博客“ Designing a Complex Leadframe Package? See How SiP Layout Tool Can…

• less than a min read
Chinese blog , SiP , SiP设计 , 引线框架 , 中文 , 封装设计 , IC封装 , SiP Layout

Academic Network

Cadence Co-organized the First EDA Competition to Help China Train More EDA Tale…

The first “China IC and EDA Design Elite Competition” started in June 2019 and received…

• 2 min read
university , Cadence Academic Network , academia , EDA

Breakfast Bytes

Off-Topic: 2019 TV Anniversaries

It's the day before a holiday. Or in this case, ten days when Cadence will be shut…

• 6 min read
off-topic

Digital Design

Library Characterization Tidbits: A Matrix for Your Reference

When working on multiple tools of the Cadence Liberate Characterization Portfolio…

• 2 min read
parameter , Liberate AMS , Matrix , liberate blog , Liberate LV , Commands , Liberate Variety , Liberate MX , Liberate , Liberate Characterization Portfolio

Breakfast Bytes

IEDM 2019: An Overview...Plus the Future of EUV

IEDM, the International Electron Devices Meeting, took place last week. It was also…

• 6 min read
EUV , IEDM

Analog/Custom Design

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization…

2019 was quite an eventful year for Virtuoso  ADE Product Suite and Virtuoso  Visualization…

• 4 min read
ADE waveform window , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler
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