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Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P
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Blog - Post List
Latest blogs

Breakfast Bytes

Barefoot in a CloudBurst: Tempus on 2000+ CPUs

Barefoot Networks gave a couple of presentations at the recent CDNLive Silicon Valley…

• 5 min read
CDNLive , barefoot networks , cloudburst , cadence cloud , CDNLive Silicon Valley

Breakfast Bytes

Driving Dangerously

I've written a few times before about the fragility of neural networks, for example…

• 5 min read
Automotive , deep learning , tesla , ADAS , neural networks

Breakfast Bytes

Sunday Brunch Video for 7th April 2019

https://youtu.be/DUu3M30lilE Made at CDNLive Silicon Valley (camera Sean) Monday…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Chiplets——重新定义系统设计

当下，电子行业经历着系统设计的新范式转变：传统的单片SoC电子系统设计思路正逐渐转变为使用chiplets（即“小芯片”）和高级封装技术的多芯片设计方法。这种逆转思维为系统设计开启了一个新的时代…

• less than a min read
SI , PI , Chinese blog , 电源完整性 , chiplets , 异质集成 , 中介层提取 , 系统设计 , IC封装设计 , 多芯片设计 , 高级封装 , 基于chiplets的系统 , 中文 , Sigrity , 信号完整性

The India Circuit

Simple Things You Can Do To Get Ahead In The Workplace

Recently we were lucky to have two of the women vice presidents at Cadence – Karna…

• 3 min read
International Women's Day , Women at Cadence , Cadence India , women leaders

Breakfast Bytes

RSA: Public Interest Technologists

Yesterday, I wrote about the first half of Bruce Schneier's keynote at the recent…

• 7 min read
security , policy , schneier

Analog/Custom Design

Virtuoso Video Diary: Checking EM Compliance Before Creating Layouts

How about checking your designs for electromigration (EM) compliance before creating…

• 2 min read
EAD , electromigration , ICADVM18.1 , electrically-aware design flow , Virtuoso electrically-aware design flow , EM , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

RSA: Bruce Schneier

I have been following Bruce Schneier for a long time. He literally wrote the book…

• 5 min read
security , public interest technology , rsa , schneier

Academic Network

Best Paper Award at LATS2019 for Zhan Gao

The IEEE Latin-American Test Symposium (LATS) is an annual forum attended by professionals…

• 2 min read
Cadence Academic Network , academia , CDNLive EMEA , modus , imec

System, PCB, & Package Design 

BoardSurfers: Validating Your Shapes

Your design is near completion. Except that you’ve got an area of your plane shape…

• 5 min read
PCB Editor , PCB design and layout , Shape Checks , Allegro

Breakfast Bytes

Geoff Hinton, Yann LeCun, and Yoshua Bengio Win 2019 Turing Award

This year's Alan Turing Award goes to Geoff Hinton, Yann LeCun, and Yoshua Bengio…

• 4 min read
deep learning , turing award , neural networks , AI

Whiteboard Wednesdays

Whiteboard Wednesdays - When it Comes to Cloud-Based Design, One Size does Not Fit…

In this week's Whiteboard Wednesdays video, Tom Hackett describes how different types…

• less than a min read
Whiteboard Wednesdays , Cloud-based Design , cadence cloud

Breakfast Bytes

Bringing Clarity to System Analysis

Today, at CDNLive Silicon Valley, Lip-Bu Tan, Cadence's CEO, announced the Clarity…

• 4 min read
system analysis , 3d field solver , cloud , cadence cloud , Sigrity , clarity

Verification

Cadence Announces Continued Partnership With Northrop Grumman

On March 28th, 2019, Cadence Design Systems announced an expanded collaboration with…

• 1 min read
chip design , Functional Verification , press release , Northrop Grumman

Verification

Cadence Leads the Pack: The First VIP for USB4 is Here!

On March 14th, Cadence announced the release of the industry’s first USB4-supporting…

• 1 min read
Functional Verification , VIP , usb4 , press release

Breakfast Bytes

CloudBurst: The Best of Both Worlds

I think if you were starting a new semiconductor company, you would go straight for…

• 3 min read
cloud , cloudburst , cadence cloud

Breakfast Bytes

Sunday Brunch Video for 31st March 2019

https://youtu.be/2_zmjd8wM0c Made on my balcony (camera Carey Guo) Monday: AI Index…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Cadence专家培训计划正式启动

感谢您对Cadence的关注与支持，我们的微信服务号“Cadence楷登PCB及封装资源中心”已正式上线。我们遵循Cadence所倡导的 “系统设计实现” 策略助力工程师们优化设计…

• less than a min read
Chinese blog , 中文

定制IC芯片设计

Virtuosity: 交互辅助布线命令的快捷键使用指南

摘要： 对于使用快捷键（bindkeys）的好处，相信您在日常工作中已深有体会。 那么，为了帮助用户获得更好的体验，本文介绍了Virtuoso 交互辅助布线相关的常用快捷键…

• less than a min read
Interactive Routing , Chinese blog , Create Wire , ICADVM18.1 , custom/analog , Virtuoso Space-based Router , Create Stranded Wire , Interactive and Assisted Routing , Wire Editing , Mixed-Signal , Virtuoso , Virtuosity , Virtuoso Video Diary , Custom IC Design , Create Bus , Custom IC , IC6.1.8 , Virtuoso Layout Suite XL
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