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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Verification community comes together to talk tech

I just finished the week at Cadence's CDNLive User Group in San Jose. Over the past…

• 1 min read
SystemVerilog , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Formal Analysis , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , ISX (Incisive Software Extensions) , Simulation acceleration , coverage driven verification (CDV) , ISX , eRM , System Verification

Verification

A few thoughts on CDNLive! and OVM 2.0

My colleague Joe Hupcey has been keeping you informed and entertained with information…

• 1 min read
CDNLive San Jose 2008 , OVM 2.0

Verification

OVM 2.0 -- Short Technical Review

By now you may have seen the official announcement of the OVM 2.0 release . So what…

• 3 min read
SystemVerilog , Verification methodology , OVM , CDV , System Verification , OVM 2.0

Verification

Day 3 of CDNLive San Jose

Highlights of Day 3: papers all morning, lunch, then closing remarks. Comments on…

• less than a min read
verification strategy , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , ISX

Digital Design

Running SoC-Encounter...from an iPhone

Hello from CDNLive Silicon Valley 2008! I've had a great few days out here interacting…

• less than a min read
SoC-Encounter , iPhone Cisco VPN Client , Mocha VNC Lite , iPhone

System, PCB, & Package Design 

CDNLive! Track 8 - The Place to Be!

Lively presentation on IBIS-AMI modeling, multi-gigabit package design, 3D field…

• less than a min read
CDNLive , cadence , SPB , SPB16.2 , wirebond profile library , Kulicke & Soffa

Verification

Day 2 of CDNLive San Jose 2008

Highlights of Day 2: more great papers (with enough customer papers on OVM fill almost…

• less than a min read

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 3 ... Product Roadmaps, More Presentations, and Poker…

From the floor of CDNLive! 2008 - San Jose Each day continues to show the value that…

• 2 min read
CDNLive! 2008 , PCB design

Verification

Day 1 of CDNLive San Jose 2008

Suffice to say, Day 1 was quite a full day, with the highlight for me being some…

• less than a min read
AMS , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , multi-language

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 2 ... Welcome, Keynote Speakers, Presentations

From the floor of CDNLive! 2008 - San Jose Wow! What an exciting, power packed, and…

• 1 min read
CDNLive! 2008 , PCB design , Michael Catrambone

Verification

Enterprise Verification gets a boost (a big one!)

Today we announced important new metric-driven verification capabilities in our enterprise…

• less than a min read
Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV) , IES

Verification

"Day 0" of CDNLive San Jose 2008

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was…

• 1 min read
CDNLive San Jose 2008 , MDV techtorial , System Verification

Verification

CDNLive SJ - system design and verification - don't miss it

If you are a system validation/verification engineer, an architect, a power engineer…

• 1 min read
Low Power , power engineer , system validation/verification engineer , embedded SW engineer , architect

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 1 ... from the Techtorials!

From the floor of CDNLive! 2008 - San Jose The first day, is always considered the…

• 1 min read
PCB Layout and routing , CDNLive , DEHDL , SPB16.2 , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , CDNLive! , Allegro PCB Editor , ConceptHDL

Digital Design

Need for dynamic IR drop analysis at floor and power planning stages?

Here is a question for all the power grid designers out there: Do you see the need…

• 1 min read
dynamic rail analysis , Early Rail Analysis , Cadence Encounter Power System , Digital Implementation

Analog/Custom Design

CDNLive Techtorials: Everything you wanted to know about Virtuoso

Hey folks, if you are coming to the CDNLive conference, we have a lot of great "techtorials…

• less than a min read
RF design , CDNLive Techtorials , custom design technology

Verification

See you at CDNLive San Jose next week

FYI, Mike Stellfox and I will be at CDNLive San Jose next week. In addition to reporting…

• less than a min read
Functional Verification , OVM , ISX (Incisive Software Extensions) , IES

Verification

Chip Level Verification with Processors

Today, I will discuss some alternatives for chip-level verification with designs…

• 6 min read
verification strategy , Functional Verification , ISX , ARM , FPGA: DMA

Digital Design

Effectively communicating Low-Power and Power-Efficient Design knowledge

For those of you interested in the Power space I recently had an article published…

• less than a min read
Low-Power , Power-Efficient Design , Logic Design , Digital Implementation
CDNS - Fix Layout Hompage