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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Computational Fluid Dynamics

VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Techn…

Hydrofoils have unleashed the speed of sailing boats since the last two America’s…

• 4 min read

定制IC芯片设计

Virtuosity: 过滤波形

在接下来的几周内，Virtuosity和Virtuoso Video Diary博客将重点关注 Virtuoso®ADE Assembler , Virtuoso…

• less than a min read
Chinese blog , ADE Explorer , plotting , plot , Filtering , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler

Breakfast Bytes

Carry: Electronics

The last two days I have written about carry in mechanical calculating devices. See…

• 7 min read
carry , adder

Whiteboard Wednesdays

Whiteboard Wednesdays - Cloud-Hosted Design Solution – a Full-Service Cloud Offe…

In this week's Whiteboard Wednesdays video, Jeff Critten describes the key benefits…

• less than a min read
Cloud-Hosted Design , Whiteboard Wednesdays , cadence cloud

Verification

AMBA Adaptive Traffic Profiles: Addressing The Challenge

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components…

• 4 min read
Adaptive Traffic Profiles , Performance modeling , AMBA , ATP

System, PCB, & Package Design 

BoardSurfers: Look Before You Leap - Verifying Footprints in the Design Capture …

View the footprints of symbols during design entry in Capture: verify the footprint…

• 2 min read
Capture CIS , PCB Editor , footprint viewer

System, PCB, & Package Design 

IC Packagers: Balance Your Designs with Cadence SiP Layout

As designs get more complicated, package substrates are seeing more silicon-driven…

• 8 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

Carry: Babbage's Engines

Yesterday's post Carry: From Logarithms to Mechanical Calculators talked about how…

• 4 min read
carry , analytical engine , difference engine , Babbage

定制IC芯片设计

Virtuoso视频日记：创建和预览激励

在接下来的几周内，Virtuosity和Virtuoso视频日记博客将重点关注 Virtuoso® ADE Assembler , Virtuoso® ADE Explorer…

• less than a min read
Chinese blog , ADE Explorer , stimuli form , stimuli , Virtuoso Analog Design Environment , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler

Breakfast Bytes

Carry: From Logarithms to Mechanical Calculators

I hope you had a great July 4th long weekend if you are in the US...and if you were…

• 6 min read
carry , ripple carry

Breakfast Bytes

Sunday Brunch Video for 7th July 2019

https://youtu.be/re7U6Rg0MHA Made at Cadence charge station (camera Sean) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

IC Packagers: Vary Your Assembled Packages, Not Your Databases

Design variants are a common phenomenon, whether you design package substrates or…

• 7 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

Off-topic: Geography

It's the day before a holiday so Breakfast Bytes goes completely off-topic as usual…

• 4 min read
offtopic

System, PCB, & Package Design 

BoardSurfers - Guest Roll: Anatomy of a Good Testcase

Rik Lee, the author of today's post, is a PCB Designer with more than 35 years experience…

• 5 min read
APD , PCB Editor , SiP Layout

System, PCB, & Package Design 

DATA Pulse: Know How to Effectively Manage Part Obsolescence (Part 2 of 2)

In part 1 of this two-part blog post, we analyzed how you can define a parts lifecycle…

• 1 min read
Library and design data management , EDM , PCB design

Breakfast Bytes

It's Beyond HOT at ES Design West Next Week

There are two famous parties in the EDA world. The Denali Party by Cadence, of course…

• 4 min read
semicon west , semi , HOT , hot party , es design west

Analog/Custom Design

Virtuoso Meets Maxwell: TILP! What’s a TILP?

I have been breathing IC layout design for the last 38 years! Proliferating new Cadence…

• 4 min read
PCells , Virtuoso Meets Maxwell , Virtuoso RF , Independent , Solution , Multitech , TILP , Custom IC Design , Virtuoso Layout Suite , technology

Breakfast Bytes

NXP: Self-Driving Cars: What's the Payoff for Carmakers?

I recently attended NXP's Silicon Valley event called NXPConnect. Kurt Sievers, the…

• 9 min read
Automotive , autonomous driving , ADAS

Breakfast Bytes

Sunday Brunch Video for 30th June 2019

https://youtu.be/WhHvvmwE9Tw Made at Tsukuda Fruit Stand opposite building 9 (camera…

• less than a min read
sunday brunch
CDNS - Fix Layout Hompage