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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Cadence Cloud - Fast, Painless, Proven Solutions for Cloud…

In this week's Whiteboard Wednesdays video, Tom Hackett continues his discussion…

• less than a min read
Whiteboard Wednesdays , Cloud-based Design , cadence cloud

System, PCB, & Package Design 

IC Packagers: A Classic Revisited - Ball Map Spreadsheets

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google,…

• 4 min read
APD , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Text Labels and Film Views Help Intelligent Designers

Last time, I talked about color and visibility as it relates to simplifying your…

• 5 min read
APD , Allegro Package Designer , Allegro PCB Editor , SiP Layout

Breakfast Bytes

Making Trouble in Las Vegas

For years John Cooley has organized what is called the Cooley's DAC Troublemaker…

• 10 min read
DAC , troublemaker , 56dac

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

The first blog of the series talks about features that are not new but capabilities…

• 4 min read
Trunk Trimming , Pin to Trunk , Create Wire , space-based router , Virtuoso Space-based Router , layout XL , Layout Suite , Trunk Extending , Layout L , Finish Trunk , EM Trunk Optimization , Custom IC Design

Learning and Support

Single-Stop Learning Resource for Cadence Low Power Simulation

Since 2006, low power design has evolved from simple shut off and isolation to very…

• 2 min read
low power simulation , LPS , suppport , power

Breakfast Bytes

Cadence Cloud Passport Partner Program

Last year at DAC, Cadence announced Cadence Cloud (see my post Cadence Cloud from…

• 6 min read
passport partner program , cadence cloud

Breakfast Bytes

Sunday Brunch Video for 9th June 2019

https://youtu.be/T8nSP-oElJM Made at Design Automation Conference (camera Sean)…

• less than a min read
sunday brunch

SoC and IP

SemiEngineering Article: Why IP Quality Is So Difficult to Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part…

• 3 min read
IP , cadence , IP blocks , Automotive Ethernet , ip cores , Tensilica , semiconductor IP , Design IP and Verification IP

PCB、IC封装：设计与仿真分析

线下专家培训第二站：PCB高效设计入门到进阶——第一期之设计环境准备

前言 大家好，我是Principal Customer Engagement Engineer郑凤仙，从事PCB设计行业十六年，先后受聘于Mitac、华为两家企业…

• less than a min read
PCB , 设计习惯 , 设计经验 , Chinese blog , 经验分享 , 设计总结 , PCB设计 , 设计环境 , 中文 , 专家培训

Academic Network

Carnegie Mellon University – Real World Engineering Program

Cadence San Jose was happy to host a group of undergraduate students from Carnegie…

• 1 min read
young professionals , cmu , Academic Network , university program

Analog/Custom Design

Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations…

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind…

• 2 min read
ICADV12.3 , ICADVM18.1 , EM/IR , electrically-aware design flow , Layout EAD , Virtuoso Layout EXL , Virtuoso , IC6.1.7 , IC6.1.8 , Virtuoso Layout Suite XL

Breakfast Bytes

1984 Was Published 70 Years Ago

If you work in any aspect of tech, one book that you have to have read is George…

• 4 min read
george orwell , 1984

Academic Network

Cadence Academic Network Expands to Kazakhstan

Dear reader, may I ask you, what do you know about Kazakhstan ? Do you know that…

• 2 min read
university , Cadence Academic Network , Kazakhstan

Breakfast Bytes

DAC Wednesday: Verification Lunch, Books, and Bagpipes

For my coverage of the first two days of DAC, see my posts DAC Monday: Gaming, IoT…

• 10 min read
DAC , 56dac , Design Automation Conference

Breakfast Bytes

DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali

It was the second day of DAC yesterday. If you were here, you probably saw some of…

• 6 min read
DAC , 56dac , Design Automation Conference

Whiteboard Wednesdays

Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM…

In this week’s Whiteboard Wednesdays video, Amol Borkar continues his discussion…

• less than a min read
Whiteboard Wednesdays , Vision Q7 DSP , SLAM

System, PCB, & Package Design 

IC Packagers: The (Copper) Pillars of Modern Design

Wire bonding has been around forever. Flip-chip mounting? That’s been around for…

• 7 min read
IC Packaging , IC Packaging and SiP , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to…

• 4 min read
APD , PCB Editor , PCB design , SiP Layout
CDNS - Fix Layout Hompage