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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Breakfast Bytes

8 Ways to Get the Most out of CDNLive Silicon Valley

It's CDNLive! Well, not today, Tuesday and Wednesday, April 2nd and 3rd at the Santa…

• 4 min read
CDNLive

Breakfast Bytes

AI Index

The 2018 AI Index Report , developed by scientists and researchers in the AI field…

• 4 min read
artificial intelligence , deep learning , AI

The India Circuit

The Power of 900 Million Voices

The Indian elections are coming up! In just a few weeks, the first of seven phases…

• 3 min read
VVPAT , Indian elections , Election Commission of India , EVM , electronic voting machine

Verification

Concurrent Actions in Specman

Lately we have been asked by several customers about the concurrency options in Specman…

• 2 min read
first of , Specman , Specman/e , Specman e , e , specman elite

Breakfast Bytes

Sunday Brunch Video for 24th March 2019

https://youtu.be/FFd9mncMANI Made at SEMICON China (camera Tracy Zhu) Monday: The…

• less than a min read
sunday brunch

Breakfast Bytes

RSA: The Director of the FBI

Christopher Wray, the current (and the 8th) Director of the FBI, wrapped up the opening…

• 6 min read
rsa , fbi

Verification

NVMe 2019 Developer's Conference: NVMe 1.4 Is Almost Here, and Enterprise and Cloud…

Unlike previous years, the annual NVM Express Developer’s Conference was held in…

• 2 min read
Verification IP , Enterprise , NVM Express , PCIe Gen4 , NVMe , VIP , cloud , PCIe , PCI Express , TripleCheck

System, PCB, & Package Design 

Exposing Adaptive EQ in 32 Gbps Receivers

It is no secret that serial link data rates have skyrocketed over the past 15 years…

• 1 min read
dfe , SI , FFE , DesignCon , Adaptive Equalization , AGC , IBIS-AMI , EQ , DesignCon 2019 , Signal Integrity , SerDes , Sigrity , SystemSI , Automatic Gain Control

Breakfast Bytes

#learntocode

When a few hundred journalists were laid off recently, there was a lot of activity…

• 7 min read
computer science , learntocode

Breakfast Bytes

RSA Cryptographers' Panel

One big highlight of the RSA conference is always The Cryptographers' Panel. This…

• 14 min read
security , rsa , cryptography

Analog/Custom Design

Virtuoso Video Diary: What Makes EM/IR Analysis A Significant Sign-Off Step?

This blog describes the EM and IR analyses in Virtuoso ADE as a design sign-off step…

• 3 min read
ADE Explorer , EM/IR , Power Integrity , IC layout , ADE , Virtuoso Analog Design Environment , Virtuoso Video Diary , sign-off , Custom IC Design , Custom IC , IC design , EMIR

Whiteboard Wednesdays

Whiteboard Wednesdays - 5G PHY Use Cases on B20

In this week's Whiteboard Wednesdays video, Rong Chen talks about the 5G use cases…

• less than a min read
5G , B20 , Whiteboard Wednesdays , ConnX

Analog/Custom Design

Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available

The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download…

• 3 min read
ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , ADE , Virtuoso Analog Design Environment , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Breakfast Bytes

RSA: From Helen Mirren to Tina Fey

The RSA Security Conference that took place in the first week of March was bracketed…

• 4 min read
security , rsa , cryptography

System, PCB, & Package Design 

BoardSurfers: Allegro 3D Canvas—Visualize the Board as You Design

Today’s dense and complex PCB designs require realistic 3D view to investigate the…

• 3 min read
PCB , Layout , 3D , PCB design , Allegro PCB Editor

Analog/Custom Design

Virtuosity: Maestro Plotting Templates

Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any…

• 3 min read
ICADVM18.1 , ADE Explorer , ViVA , plotting templates , maestro plotting templates , Custom IC Design , IC6.1.8 , ADE Assembler

Breakfast Bytes

The World Wide Web Was Born 30 Years Ago This Month

In March 1989 at CERN, a guy called Tim-Berners Lee had an idea about how to get…

• 4 min read
Internet , tim-berners lee , CERN

Breakfast Bytes

Sunday Brunch Video for 17th March 2019

https://youtu.be/b5eJJcHiOoY Made at Cadence building 9 lobby (camera Sean) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

Domain-Specific Computing 3: Specialized Processors

The last two days' posts have looked at the development of general-purpose processors…

• 8 min read
domain specific computing , special purpose architectures , GPUs , Dark Silicon , Tensilica , ARM
CDNS - Fix Layout Hompage