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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Breakfast Bytes

Ambit Design Systems

Twenty years ago today, Cadence announced it was acquiring Ambit Design Systems.…

• 5 min read
ambit , Synthesis , buildgates

Breakfast Bytes

Labor Day Off-Topic: Almost Everyone Has More Than the Average Number of Legs

It's Labor Day. Cadence is closed in the US. Unfortunately, I'm in India and it's…

• 5 min read
math , off-topic , mathematics

Analog/Custom Design

Virtuosity: Opening Old ADE States and Views with ADE Explorer and ADE Assembler

Have you found it a pain that when opening a Virtuoso ADE L state or a Virtuoso ADE…

• 2 min read
Explorer , ADE Migration , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Virtuosity , IC6.1.7 , Custom IC Design , Assembler

Analog/Custom Design

Virtuoso IC6.1.7 ISR22 and ICADV12.3 ISR22 Now Available

The IC6.1.7 ISR22 and ICADV12.3 ISR22 production releases are now available for download…

• 2 min read
Analog Design Environment , ICADV12.3 , ADE Explorer , ADE , Layout , Virtuoso , IC6.1.7 , Custom IC Design , Custom IC

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之1：先进的柔性和刚柔结合板设计支持

为何要刚柔结合？ 对几乎所有应用，客户一直希望能有更小、更轻、性价比更高的产品。竞争压力也促使设计工程师们以不断增长的速度将这些新产品带到市场。设计工程师们可使用柔性PCB材料…

• less than a min read
PCB , Chinese blog , Allegro 17.2 , PCB设计 , 中文 , MCAD-ECAD , IPC-2581 , Allegro PCB编辑器 , 刚柔结合设计 , Allegro升级17.2 , 刚柔结合

Breakfast Bytes

HOT CHIPS Tutorial: On-Device Inference

The Sunday of the annual HOT CHIPS (the 30th!) conference is tutorial day. In the…

• 5 min read
deep learning , inference , Tensilica , hot chips , inferene , neural networks

Breakfast Bytes

Breakfast Buffet for August

https://youtu.be/elQgyXvkcjU The three highlighted posts for August were: Two…

• less than a min read
shockley , jobs , eri , darpa

定制IC芯片设计

Virtuoso: 新序曲—设计意图工具（Design Intent）工具简介

简化设计目标， 并且给版图设计师们提供更多自由来实现他们的设计目标。

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso Design Intent , Virtuoso Schematic XL , Layout design , Constraints , Custom IC Design , Custom IC , Schematic , Virtuoso Layout Suite XL

Verification

Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much…

One animation video - Patch Like The Wind - is worth a thousand words :) If you…

• 2 min read
Specman , Specman/e , Functional Verification , Specman e , tech tips , e language , team specman , save and restart

Breakfast Bytes

Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter

At the recent HOT CHIPS conference, Scott Johnson of Google talked about some challenges…

• 6 min read
security , titan , google , supply chain , secure boot

Analog/Custom Design

Virtuosity: New Virtuoso Visualization and Analysis RAK for IC6.1.8/ICADVM18.1

We've updated the Virtuoso Visualization and Analysis Rapid Adoption Kit (RAK) for…

• 2 min read
ICADV12.3 , ICADVM18.1 , Rapid Adoption Kit , RAK , virtuoso visualization and analysis , ViVA , IC6.1.7 , IC6.1.8

Academic Network

Great Academic Networking in Taiwan - 2018 VLSI Design/CAD Symposium

Cadence Academic Network and Taiwan Marketing co-supported the annual VLSI Design…

• 1 min read
VLSI , university , Taiwan , Cadence Academic Network , Academic Network

The India Circuit

Don't Miss These 6 Things At CDNLive India 2018!

1. The Cadence keynotes: Lip-Bu Tan on Day 1 and Babu Mandava on Day 2 Apart from…

• 2 min read
CDNLive India , Babu Mandava , CDNLive , Cadence India , Lip-Bu Tan

定制IC芯片设计

Virtuoso: 新序曲-DRD推出新界面

最近几个月如果您关注Cadence 新闻的话，肯定听说了DRD重新推出的消息。让我们近距离来了解一下全新的DRD吧！

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , DRD , New in EDA , Custom IC Design , Custom IC

Breakfast Bytes

Carbon Nanotube Memory: Too Good to Be True?

One of the sessions at HOT CHIPS is on new technologies, and one of those presentations…

• 5 min read
Memory , cnt , carbon nanotube , DRAM , hot chips , nram

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Breakfast Bytes

What's For Breakfast? Video Preview September 3rd to 7th 2018

https://youtu.be/ipUI2OaAWX4 \ Coming from the old Ambit Design Systems office on…

• less than a min read
chiplets , ambit , buildgates , pcast , eri , darpa , chips

Breakfast Bytes

ImageNet: The Benchmark that Changed Everything

I like to date technical transitions from specific events, even though realistically…

• 6 min read
imagenet , gtsdb , Tensilica , CNN , neural network

Verification

Evolution of DisplayPort

In 2006, the Video Electronics Standards Association (VESA) designed a new display…

• 2 min read
Verification IP , DisplayPort , verification
CDNS - Fix Layout Hompage