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Featured

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
Corporate 11 Jun 2026 • 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
Corporate 2 Jun 2026 • 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
Corporate 31 May 2026 • 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
Corporate 21 May 2026 • 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

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Blog - Post List
Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview August 7th to 11th 2018

https://youtu.be/xPVzOfBHGlM Coming from Cadence Intern Showcase (camera Sean…

Paul McLellan 2 Aug 2018 • less than a min read

Digital Design

QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

Whenever we talk to potential customers about Stratus HLS , we usually mention that…

SeanDart 2 Aug 2018 • 4 min read
High-Level Synthesis , Stratus , SystemC , HLS

Analog/Custom Design

Virtuoso Video Diary: Single Schematic Flow in Virtuoso System Design Platform

The Single Schematic Flow in Virtuoso System Design Platform simplifies the product…

deeptig 2 Aug 2018 • 2 min read
vsdp , Virtuoso , Schematic Editor , Virtuoso Video Diary , Custom IC Design , single schematic , Schematic

Breakfast Bytes

ITF: CFETs and New Interconnect

At the imec technology forum (ITF) held the day before SEMICON West opened, two of…

Paul McLellan 2 Aug 2018 • 8 min read
3nm , cfet , ruthenium , imec , itf

Breakfast Bytes

How to Pitch a Journalist

In the early part of my career, I was an engineer or an engineering manager. Then…

Paul McLellan 1 Aug 2018 • 7 min read
journalism , marketing

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the…

References4U 31 Jul 2018 • less than a min read
Whiteboard Wednesdays , ccix , cloud

Verification

Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meet…

We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it…

XTeam 31 Jul 2018 • 2 min read
Functional Verification , DAC 2018 , Altia Systems , xcelium

Breakfast Bytes

GLOBALFOUNDRIES' CTO State-of-the-Roadmaps

At SEMICON I got to sit down with Gary Patton, the CTO of GlobalFoundries. They have…

Paul McLellan 31 Jul 2018 • 8 min read
22fdx , 12fdx , gary patton , FinFET , GlobalFoundries , FD-SOI

Breakfast Bytes

Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happines…

At SEMICON West, Dave Patterson (center) sat down for an interview with author John…

Paul McLellan 30 Jul 2018 • 6 min read
turing award , RISC , UC Berkeley , dave patterson

Breakfast Bytes

Turning Fixed Costs into Variable Costs: Foundries and Clouds

One trend that has been accelerating for a couple of decades is turning fixed costs…

Paul McLellan 27 Jul 2018 • 6 min read
EDA , cloud , cadence cloud , mobile , fixed cost

Breakfast Bytes

Breakfast Bytes Guide to Armenia

Every summer for a week I go hiking with a group of friends. We used to just go to…

Paul McLellan 26 Jul 2018 • 9 min read
yerevan , genocide , khachkar , armenia , Virage Logic

System, PCB, & Package Design 

EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 2 of 4)

In part 1 of this blog series we discussed the duality between the electrical and…

Sigrity 25 Jul 2018 • 5 min read
EE Thermal , temperature , Thermal Basics , Heat transfer , PowerDC

Breakfast Bytes

What's For Breakfast? Video Preview July 30th to August 3rd 2018

https://youtu.be/HoEoMWal_48 Coming from DARPA ERI Summit at Palace of Fine Arts…

Paul McLellan 25 Jul 2018 • less than a min read
interconnect , cfet , imec , cadence cloud , xcelium , GlobalFoundries , simulation , dave patterson

Breakfast Bytes

Trends, Technologies, and Regulations in China's Auto Market

At "Ludwigsburg", officially the International Autombil Elektronik Kongress, there…

Paul McLellan 25 Jul 2018 • 5 min read
Automotive , China , volkswagen

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the…

References4U 24 Jul 2018 • less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

Cadence Is MAGESTIC

Today at the Electronic Resurgence Initiative (ERI) Summit in San Francisco, DARPA…

Paul McLellan 24 Jul 2018 • 4 min read
magestic , idea , electronic resurgence initiative , posh , eri , darpa

Verification

Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months

Here’s something to chew on: Syntiant is an AI startup involved in deep learning…

XTeam 23 Jul 2018 • 2 min read
DAC , Functional Verification , syntiant , DAC 2018 , cadence cloud

Breakfast Bytes

Nicolas's Recipe for Digital Marketing in EDA

This is the third (and final) post about the ESD Alliance workshop on digital marketing…

Paul McLellan 23 Jul 2018 • 5 min read
digital marketing , esd alliance

Verification

Perspec Portable Stimulus Hands-On Workshop at DAC 2018

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised…

Steve Brown 20 Jul 2018 • 1 min read
Perspec , AMIQ , pss , portable stimulus
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