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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

SoC and IP

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

• 2 min read
IP , IP integration , SDE , noise , Sigrity

Breakfast Bytes

Application Engineers Are Like Gold

I wrote recently about my experiences Running a Salesforce , and one of the key aspects…

• 4 min read
application engineers

Analog/Custom Design

Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing

In order to drive high current and to minimize routing resistivity, it is desirable…

• 3 min read
interactive coloring , stranded wire , Virtuoso Space-based Router , weStrandedColorMode , leHiCreateStrandedWire , blockage avoidance , weStrandedAlignCollinearMode , Virtuoso , Stranded Wire Context-sensitive Menu , Virtuoso Video Diary , tieout , weStrandSpacing , tapering in stranded wire , Custom IC Design , WSP support in Stranded Wire , space based router , Custom IC , weStrandedLadderAtTurn , weStrandNum

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (6 of 8)

Simulating with IBIS-AMI Models By this point in the process, the SerDes component…

• 3 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Warsaw to Canary Islands to Madrid to Staten Island to California: Michal's Jour…

Some people grow up in the US, go to high school, get into a good engineering or…

• 8 min read
logical equivalence checking , LEC , Stanford , verplex , Berkeley , Poland , Formal verification

Breakfast Bytes

What's For Breakfast? Video Preview February 12th to 16th 2018

https://youtu.be/wwioFa3JGuc Coming from the Cadence basketball court (camera…

• less than a min read
PCB , pluto , packaging , patent , more than Moore , PCB design , zombie , CEO

Breakfast Bytes

Oz and Ziyad Look to the Future of JasperGold

At last year's Jasper User Group, the two-day event was opened by Oz Levia, VP of…

• 4 min read
Jasper User Group , JUG , formal , JasperGold , Formal verification , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Dual Channel DIMMs for Server Applications

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty, discusses how future…

• less than a min read
Whiteboard Wednesdays , Dual Channel DIMM , DIMM

Analog/Custom Design

Integrating AMS IP in SoC Verification Just Got Easier

Typically, analog designers verify their AMS IP in schematic driven, interactive…

• 1 min read
AMS , mixed signal solution , Mixed-Signal , analog/mixed-signal , Virtuoso , mixed signal , Virtuoso environment , mixed-signal verification

Breakfast Bytes

Fooling Neural Networks

I wrote recently about various aspects of modeling , not just transistor models,…

• 4 min read
security , neural networks , CNN

Breakfast Bytes

The Old Order Changeth: Samsung Takes the Crown

The most famous line of Tennyson's poem Morte D'Arthur is "The old order passeth…

• 6 min read
Intel , Memory , flash , Samsung , mobile

Analog/Custom Design

Virtuosity: Sharing Custom SKILL Calculator Functions

Have you ever written a fantastic piece of SKILL to carry out a calculation and wanted…

• 3 min read
Analog Design Environment , ADE Explorer , Virtuoso , ViVA , Custom IC Design , SKILL , ADE Assembler

Breakfast Bytes

DesignCon: PCB and Packaging Take Center Stage

You wouldn't really know it from the name, but DesignCon is all about the design…

• 8 min read
si/pi , EMI , DesignCon , deep learning , Power Integrity , machine learning , Signal Integrity , dnn , CNN , neural network

Verification

New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant…

• 2 min read
amba5 , ACE5 , AXI5 , AMBA

Breakfast Bytes

DesignCon: SI, PI and EMI Have a Threesome

DesignCon 2018 opened with a keynote panel on the subject of SI, PI, and EMI Challenges…

• 8 min read
DesignCon , Power Integrity , Signal Integrity , electromagnetic interference

SoC and IP

You Won't Believe Your Ears When Listening to Your Laptop

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth…

• 2 min read
CES , audio , HiFi , Tensilica

Breakfast Bytes

Open-Source IP in Government Electronics

At the RISC-V conference late last year, one of the keynotes was by Linton Salmon…

• 6 min read
risc-v , dod , darpa

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4X DRAM: Performance and Power Efficiency Improvements…

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty will help you learn…

• less than a min read
Whiteboard Wednesdays , LPDDR4

Breakfast Bytes

All Models Are Wrong; Some Are Useful

"All models are wrong, some are useful.” This remark is attributed to the statistician…

• 9 min read
climate , model , digital , SPICE
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