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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Verification

JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive…

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification…

• 1 min read
Verification IP , UniPro , MIPI Alliance , JEDEC , automotive electronics , UFS , storage , MPHY

Breakfast Bytes

TSMC 30 Years Ago Today

At IEDM in December, Gary Dagastine is one of the people responsible for press relations…

• 6 min read
Taiwan , fabless , TSMC , chips and technologies , foundry

The India Circuit

The Promise Of Digital India

By 2019, it is estimated that there will be five billion mobile phone users in the…

• 4 min read
Narendra Modi , digital india , National Digital Literacy Mission , Aadhar , Ravi Shanker Prasad

Breakfast Bytes

City Slickers Marketing

Last week I talked about sales in Running a Salesforce . This week it is the turn…

• 4 min read
steve blank , city slickers marketing , marketing

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Challenges for SoCs Integrating CCIX Interface…

In this week's Whiteboard Wednesdays episode, Nick Heaton, Distinguished Engineer…

• less than a min read
Whiteboard Wednesdays , ccix

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE/Marine for various…

• 3 min read

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE /Marine for various…

• 4 min read

Breakfast Bytes

Coventor Annual Panel: The Next Five Years

For the last few years at IEDM, Coventor have run an evening panel session looking…

• 8 min read
asml , KLA-Tencor , Lam Research , nova , Coventor , GlobalFoundries , IEDM

Verification

Type MIN / MAX Values in Specman

When defining coverage bins for coverage items, the number and size of bins depend…

• 3 min read
Specman , Specman coverage engine , Specman e

Verification

App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains…

• 1 min read
SystemVerilog , real number modeling , Functional Verification , App Note Spotlight

Verification

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
Verification IP , ccix , SoC , coherency , System Verification

Breakfast Bytes

Passwords: Just Add Salt

This is a second post about passwords, picking up where Passwords: How Even Your…

• 5 min read
security , password , two-factor authentication , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview January 29th to February 2nd 2018

https://youtu.be/OtFTlu1u9xI Coming from TSMC North America (camera Sean) Monday…

• less than a min read
DesignCon , Models , TSMC , semiconductor IP , open source

Breakfast Bytes

Passwords: How Even Your Bank Doesn't Know Your PIN

In my predictions for 2018 piece yesterday, Nibbles: Breakfast Bytes Predictions…

• 7 min read
cryptographic hash , passwords , salt , hashing

Breakfast Bytes

Nibbles: Breakfast Bytes Predictions for 2018

Every year Breakfast Bytes makes some predictions for the year. At the end of the…

• 7 min read
security , Automotive , 5nm , autonomous vehicles , EUV

Analog/Custom Design

Virtuosity:Expression Builder - Now Plots ALL!

The Expression Builder has simplified writing complex expressions and has the ability…

• 2 min read
ADE Explorer , ADE , Expression Builder , Virtuoso , ViVA , Virtuosity , ADE Assembler

Breakfast Bytes

Running a Salesforce

I decided to run some posts on different areas of companies, and what I have found…

• 10 min read
sales , salesforce , business development , sales management

System, PCB, & Package Design 

Designing Data Bus with DDR5 Technology Today? Yes, It Is Possible!

Many system designers have been working with DDR4 RAM components in the past couple…

• 4 min read
ddr5 , AMI , Memory interface , IBIS , IBIS-AMI , DDR , Sigrity

System, PCB, & Package Design 

Improve High-Speed Serial Link Design with IBIS-AMI Backchannel Simulation

As signal integrity engineers, we know adaptive equalization is used in today’s multi…

• 3 min read
Serial link analysis , Backchannel Simulation , IBIS-AMI , SerDes , Sigrity , SystemSI
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