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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar continues his explanation of…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

Virtuoso System Design Platform Is Product of the Year

The title of this post says it all, but I'd better add a bit of color. Cadence was…

• 5 min read
virtuoso system design platform , Virtuoso , Allegro

Breakfast Bytes

2017: A Year in Breakfasts

So 2017 is over. Taylor Swift got into trouble for saying it was a great year and…

• 6 min read
security , Automotive , risc-v , nanosheet , broadcom , Qualcomm , 5nm , nanowire

Verification

Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review

It’s always good to hear what real users think of products. Here is a very detailed…

• 3 min read

Verification

Register for the UVM Register Layer Webinar on January 12!

On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim…

• less than a min read
webinar , Doulos , xcelium , uvm register layer

Breakfast Bytes

GLOBALFOUNDRIES 7nm

Earlier in the week, I wrote about my meeting with Gary Patton the day before GLOBALFOUNDRIES…

• 3 min read
GlobalFoundries , 7nm , EUV , IEDM

Analog/Custom Design

Automatically Reusing an SoC Testbench in AMS IP Verification

The complexity and size of mixed-signal designs in wireless, power management, automotive…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal solution , analog , Mixed-Signal , analog/mixed-signal , Virtuoso environment , mixed-signal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (4 of 8)

Enabling Constraint-Driven Design With the pre-layout testbench built, populated…

• 5 min read
Serial link analysis , SI , Constraint Driven Design , Multi-Gigabit , PCIe , Signal Integrity , Sigrity

Breakfast Bytes

CES18 Preview

It's the start of a new year and that means it is the Consumer Electronics Show in…

• 9 min read
ces 2017 , deep learning , CES , audio , inception , atmos , Dolby , Tensilica , vision , neural networks

Breakfast Bytes

What is Meltdown? How Can It Affect Both Intel and Arm?

If you pay attention to anything to do with processors, security, or even investment…

• 8 min read
security , Intel , meltdown , x86 , ARM

Breakfast Bytes

What's For Breakfast? Video Preview January 8th to 12th 2018

https://youtu.be/txCnT3N4OSY Coming from Executive Briefing Center (camera Sean…

• less than a min read
Consumer Electronics Show , CES , CES2018 , semi , Virtuoso , ARM

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (3 of 8)

IBIS-AMI Modeling With initial PCB trace and via models in place for our hypothetical…

• 2 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Gary Patton on GF, IBM, 7nm, EUV, and More

At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss…

• 8 min read
fab8 , 7lp , 12fdx , gf , gary patton , malta , 12lp , GlobalFoundries , 7nm

The India Circuit

Face Recognition and Hackathon: An Unlikely and Innovative Combination

Happy New Year! While most other folks are just easing back to work, those of us…

• 4 min read
VLSI & Embedded Systems Design Conference , Tensilica , Tensilica Xtensa , neural networks , CNN , face recognition

Breakfast Bytes

Intel 10nm

At IEDM last month, Intel announced details of their 10nm process. Later the same…

• 5 min read
Intel , coag , FinFET , 10nm , Breakfast Bytes

Breakfast Bytes

Frankenstein

"Hail to thee, blithe spirit! Bird thou never wert"...and Frankenstein. What do these…

• 3 min read

Breakfast Bytes

What's For Breakfast? Video Preview January 1st to 5th 2018

https://youtu.be/Xja6H1meqac Coming from Yosemite National Park (camera Carey…

• less than a min read
Intel , ces 2017 , Consumer Electronics Show , CES , GlobalFoundries , 7nm , 10nm

Breakfast Bytes

Why Don't Planes Obey Moore's Law?

In my post about Silexica ( Silexica: Mastering Multicore ) I said that I like to…

• 9 min read
great flight diagram , aeronautics , tennekes , flight , simple science of flight

Analog/Custom Design

Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

“The reason birds can fly and we can't is simply because they have perfect faith…

• 2 min read
Cadence blogs , Virtuoso , RF design , Virtuosity , Virtuoso Video Diary , CPG Technical Communications Engineering
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