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Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - The Future of Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen looks at the future of neural…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural networks

Breakfast Bytes

Open Server Summit: How to Install 5,000 Servers Per Day

There are only a few end markets for semiconductors that really drive the technology…

• 6 min read
Open Server Summit , servers , datacenter

Verification

Building Efficient Scoreboards

A “scoreboard” is a verification component that checks the data sent to the DUT against…

• 7 min read

Breakfast Bytes

"Interoperability is the Only Way to Prove Standards Compliance"

At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi…

• 3 min read
pcie 4.0 , data center , PHY , mellanox , PCIe , mobile , PCI Express

Breakfast Bytes

Memory in China: XMC

Yesterday I covered the first half of the CASPA meeting last Saturday about memory…

• 4 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Verification

RTL Signoff vs. Functional Signoff

The notion of signoff has many layers to it, both in terms of complexity but also…

• 4 min read
funtional verification , IMC , metric driven verification (MDV) , functional coverage , MDV , vManager

Breakfast Bytes

Memory, the Turning Point of Chinese Semiconductor Industry

I can't keep away from work. Saturday found me in the Cadence auditorium for the…

• 5 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Breakfast Bytes

TI and UI: Texas Instruments' Experience with the Common User Interface

Cadence's tools Genus, Innovus, and Tempus have a lot of functionality in common…

• 3 min read
Genus , Tempus , Joules , Voltus , Innovus , Bob Sussman , Texas Instruments , TI , Breakfast Bytes , common UI

Whiteboard Wednesdays

Whiteboard Wednesdays - Common Infrastructure Between Simulation VIP and Accelerated…

In this week's Whiteboard Wednesdays video, Arindam Guha discusses the common infrastructure…

• less than a min read
accelerated VIP , Verification IP , simulation VIP , simulation

Academic Network

Cadence Participates in 14 Spring Career Fairs

Rain or snow does not stop our Cadence employees from being the perfect brand ambassadors…

• 1 min read
university , Cadence Academic Network , campus recruitment , academia

System, PCB, & Package Design 

What's Good About the latest RF PCB? New capabilities in 16.6-2015!

The 16.6-2015 RF PCB release contains many new features and updates. Read on for…

• 4 min read
RF , Cadence Design Systems , 16.6 , SPB , Grzenia , Allegro

Breakfast Bytes

Qualcomm Looks to the Future: Steve Mollenkopf's CDNLive Keynote

Steve Mollenkopf, the CEO of Qualcomm Incorporated, gave one of the keynotes at CDNLive…

• 4 min read
mollenkopf , CDNLive , IoT , Qualcomm , Internet of Things , drone , mobile , Snapdragon , CDNLive Silicon Valley , ARM , datacenter , Breakfast Bytes

Verification

Modelling a Value Holder Template with the Value “new-ed” by Default

In many companies, there is a well-defined flow for handling monitored data items…

• 2 min read
IEEE 1647 , Specman , tech tips , e , e language , specman elite , Aspect Oriented Programming , AOP , verification

Breakfast Bytes

Jim Hogan and the Early Days of Virtuoso

I had lunch with Jim last week to get a little color on the early days of the Virtuoso…

• 3 min read
Hogan , james spoto , national , Virtuoso , daisy systems , chipmaster , Jim Hogan , SDA , SKILL

Academic Network

Announcement of MEMS Design Contest at DATE

On March 17 th in the Exhibition Theatre at DATE, there was the first public announcement…

• 3 min read
Cadence Academic Network , academia , MEMS Design Contest

Breakfast Bytes

AdaptIP Talk About Their High-Level Synthesis Approach at CDNLive

At this year's CDNLive, AdaptIP presented their experiences with high-level synthesis…

• 4 min read
802.11ah , CDNLive , adaptip , Stratus , viterbi decoder , high level synthesis , CDNLive Silicon Valley , FFT , HLS , Breakfast Bytes

Analog/Custom Design

Virtuosity: Things I Learned in January, February, and March 2016 by Browsing Cadence…

At CDNLive Silicon Valley this month, Cadence announced a new family of ADE tools…

• 6 min read
verifier , Explorer , Advanced Node , ADE , modgens , Assembler , VLS XL

Academic Network

What Are Rapid Adoption Kits, And Why Are They Great for Academia?

Academic research often requires the learning of new concepts and techniques in a…

• 1 min read
Cadence Academic Network

Breakfast Bytes

Tom Beckley's CDNLive Keynote: Addressing Complexity and Safety Challenges

Tom Beckley gave the final keynote before lunch here at CDNLive in Silicon Valley…

• 3 min read
Virtuoso Variation Option , Virtuoso ADE Verifier , Tom Beckley , CDNLive , CDNLive Silicon Valley 2016 , Virtuoso , CDNLive Silicon Valley , Virtuoso ADE Explorer , Virtuoso ADE Assembler , Breakfast Bytes
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