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The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Breakfast Bytes

Mobile Unleashed...and Reviewed

I finished reading Don Dingee and Dan Nenni's book, Mobile Unleashed, the Origin…

• 5 min read
Apple , Simon Segars , Samsung , Qualcomm , mobile , ARM processors , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Relationships Between USB Specs

In this week's Whiteboard Wednesdays video, Jacek Duda describes the relationships…

• less than a min read
USB Power Delivery , Whiteboard Wednesdays , IP , USB Type-C , Jacek Duda , USB , USB-C , USB 3.1

Analog/Custom Design

Analog Design Resonance: Getting Started with Virtuoso ADE Explorer and Assemble…

By now, you have probably heard about the new family of Virtuoso ADE tools, publicly…

• 2 min read
Analog Design Environment , ADE XL , ADE , Virtuoso , IC6.1.7 , Custom IC Design

Analog/Custom Design

Welcome to the New Sound of Analog Design

The new Virtuoso ® ADE product suite enables designers to fully explore, analyze…

• 2 min read

Breakfast Bytes

Happy 25th Birthday, Virtuoso!

There are a lot of changes going on in the environment in which analog design gets…

• 5 min read
Virtuoso Variation Option , Virtuoso ADE Verifier , Virtuoso , analog design , Virtuoso ADE Explorer , Virtuoso ADE Assembler , Breakfast Bytes

Breakfast Bytes

A Brief History of Cadence: the Present Day

In the early days, like all the larger EDA companies, Cadence grew through a mixture…

• 3 min read
cadence , startups , history , SDA , acquisitions

Breakfast Bytes

Blue Gecko, Designed with Cadence Mixed-Signal, Low-Power Flow

Blue Gecko is a system on chip (SoC) created by Silicon Labs to provide wireless…

• 1 min read
AMS , Tempus , Silicon Labs , blue gecko , Voltus , bluetooth , Spectre , Innovus , mixed signal , zigbee

Academic Network

Student Day at embedded world, Nuremberg

The Cadence Academic Network was proud to sponsor the Student Day at embedded world…

• 1 min read
Student Day , Cadence Academic Network , Embedded World

Breakfast Bytes

EDAC Becomes the Electronic System Design Alliance

Last night, Bob Smith, the executive director of what was EDAC, announced the new…

• 5 min read
robert smith , ESDA , semi , embedded software , bob smith , Semiconductor , semiconductor IP , EDAC , Breakfast Bytes , esd alliance

SoC and IP

Design IP Customer and Technology Presentations at CDNLive Silicon Valley, April…

We have an exciting Design IP track at CDNLive Silicon Valley again this year. ARM…

• 1 min read
Design IP , CDNLive , PCIe Gen4 , DIP , SerDes , Silicon Valley

Analog/Custom Design

Welcome to TeamADE

Welcome to the new home of all things related to the Virtuoso® Analog Design Environment…

• less than a min read
custom design , Virtuoso Analog Design Environment , Virtuoso , analog design

Breakfast Bytes

Memory Standards and the Future

I sat down and talked with Amjad Qureshi recently He is vice president of research…

• 3 min read
Memory , DDR4 , LPDDR4 , JEDEC , HBM , Denali , DDR , amjad qureshi

Whiteboard Wednesdays

Whiteboard Wednesdays - Memory Trends to Fit Your Application

In this week’s Whiteboard Wednesdays video, Jeffrey Chung talks about the progression…

• less than a min read
Design IP , LPDDR , memory IP , DDR

Breakfast Bytes

Encryption: Why Backdoors Are a Bad Idea

I have always had a passing interest in encryption and security. My PhD is on network…

• 7 min read
vlsi technology , imessage , Apple , clipper , encryption , iOS , granitephone , backdoor , Breakfast Bytes

System, PCB, & Package Design 

What's Good About the Latest System-In-Package (SiP)? New Capabilities in 16.6-2015…

Several new features have been added to the 16.6-2015 SiP release. Read on for more…

• 4 min read
IC Packaging and SiP Design , Cadence Design Systems , SiP , IC Packaging , Allegro 16.6 , Digital SiP design , Grzenia , Allegro

Verification

How to Handle a Binding Catastrophe

Are you busy debugging your environment topology and coming up against components…

• 3 min read
Specman , TLM , binding

Breakfast Bytes

A Brief History of Cadence: the Post-Costello Years

Through the 1990s, Cadence made lots of smaller acquisitions. In 1997, Joe Costello…

• 2 min read
Costello , cadence , Bingham , Lip-Bu Tan , mergers , history , fister , Harding

SoC and IP

Tech Shanghai Drives Innovation by Overcoming Challenges

Far more often than we imagine, we think about China within the context of the complicated…

• 2 min read
China , DDR4 , PCIe Gen4 , tech shanghai

System, PCB, & Package Design 

Reports – Now Sorting Your Strings the Way YOU Want Them Sorted

When it comes right down to it, if we asked most of you what was the most important…

• 4 min read
documentation , Cadence Design Systems , Reports , manufacturing exports , APD , Allegro Package Designer , IC packaging documentation , SiP Layout , sorting
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