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Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai
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Blog - Post List
Latest blogs

SoC and IP

Just what does “XXnm-class” mean for NAND Flash devices? Why the smoke? Why the mirrors…

Two days ago, I posted a short blog entry on Hynix’s new “20nm-class” 64Gbit NAND…

• 2 min read

Verification

e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages…

• 1 min read
IEEE 1647 , funtional verification , when sub-typing , TLM , Verification methodology , Object Oriented Programming , innovation , Functional Verification , Open Verification Methodology , when inheritance , Testbench simulation , OVM e , Coverage-Driven Verification , e , OVM-e , team specman , specman elite , OOP , coverage driven verification (CDV) , ClubT , Aspect Oriented Programming , esl tlm synthesis rtl dac estimation planning , macros , eRM , System Verification , Incisive Enterprise Simulator (IES) , hvl , IES , Coverage Driven Verification , Functional Verificatioa , OVMWorld , verification , IES-XL , Trailblazer

Digital Design

Abstracts For CDNLive! Silicon Valley 2010 Due August 22

Don't let the name CDNLive! confuse you. It's the Cadence user's group conference…

• 2 min read
Floorplanning , hierarchical design , Digital Implementation , CDNLive! , tcl

SoC and IP

Hynix initiates “20nm-class” NAND Flash production with 64Gbit devices

Hynix announced yesterday that it has begun mass production of 64Gbit NAND Flash…

• 1 min read

Digital Design

EDA Follow-The-Leader ... Signoff In The Design Flow

As a member of the EDA community, I find it interesting and somewhat frustrating…

• 1 min read

Verification

e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification…

• 2 min read
IEEE 1647 , funtional verification , IntelliGen , Specman , methodology , Object Oriented Programming , Functional Verification , Open Verification Methodology , specman job postings , OVM e , Incisive , jobs , e , OVM-e , team specman , specman elite , OOP , job postings , Aspect Oriented Programming , eRM , IEV , System Verification , Incisive Enterprise Simulator (IES) , hvl , AOP , IES-XL , Trailblazer

Verification

TLM-driven Design And Verification Methodology Book Author Interviews

The recently published TLM-driven Design and Verification Methodology book has been…

• less than a min read
TLM , methodology , Stellfox , Balarin , Mosenson , Bailey , Watanabe , McNamara , ESL , book

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL Test Setup

In my last post , I left you in suspense, with your mouse hovering over the words…

• 4 min read
IC 6.1 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Memcon 2010 proceedings now online

Last week’s MemCon 2010 was a blowout event, focusing on the past, present, and future…

• less than a min read

SoC and IP

The Woz Is Coming...The Woz Is Coming...The Woz Is Coming...and keynoting at the…

Just announced, Steve Wozniak will be speaking at the Flash Memory Summit this month…

• less than a min read

System, PCB, & Package Design 

What's Good About The PCB SI Model Editor? See For Yourself In The SPB16.3 Release

With the SPB16.3 release of PCB SI , the Model Editor has been added to allow you…

• 5 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , HSPICE , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB design , SI analysis and modeling , model editor , power

SoC and IP

Real comments on SSDs from the industry at large over at LinkedIn

It’s easy for pundits to flap their lips when speaking about SSDs. What’s harder…

• 4 min read

SoC and IP

I’ve been waiting for this: water-cooled DDR3 SDRAM from Kingston

Long, long ago in a galaxy far, far away--PC motherboards carried an array of chips…

• 2 min read

SoC and IP

Motley Fool investment site discovers SSDs, gets it wrong

The Motley Fool, a famous investment book turned Web site ( www.fool.com ) just posted…

• 2 min read

SoC and IP

DRAMeXchange says DRAM market topped $10 billion in Q2

The worldwide market for DRAMs exceeded $10 billion in Q2 according to David Manners…

• 1 min read

Verification

Silicon Hive CTO: How Transaction-Based Acceleration Speeds IP Verification And Prevents…

Jeroen Leijten is Chief Technology Officer for Silicon Hive , a Dutch company that…

• 7 min read
IP , Leitjen , Acceleration , Silicon Hive , video , Palladium , SoC , Emulation , transaction-based , TBA , graphics , verification

Verification

Do Hardcopy Books Still Have Value?

As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just…

• 2 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera , VMM

Verification

Tech Tip: Dramatically Improve Throughput With “Assertion Distributor”

There are several ways that Incisive Formal Verifier (IFV) can be set to evaluate…

• 4 min read
ABV , Functional Verification , vPlan , Fornal , Desktop Manager , IEV , IFV

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Assembly Rule Checks

This is the third in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , package , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa
CDNS - Fix Layout Hompage