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Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
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Blog - Post List
Latest blogs

Academic Network

Taiwan National IC Design Competition

The Taiwan National IC Design Competition was a great opportunity for Cadence and…

• 1 min read
Taiwan , Cadence Academic Network , academia , EDA

Whiteboard Wednesdays

Whiteboard Wednesdays - Announcing Celsius Thermal Solver: A New Approach to System…

In this week's Whiteboard Wednesdays video, Be Gu introduces Celsius Thermal Solver…

• less than a min read
celsius , Whiteboard Wednesdays , Thermal Analysis , finite element analysis , FEA

System, PCB, & Package Design 

BoardSurfers: PCB Electronics - Defining and Applying Physical and Spacing Const…

If you get frequent calls from your fab houses or your customers regarding your product…

• 6 min read
APD , PCB Editor , Constraint Manager

Digital Design

Upcoming Webinar: AI Accelerator Design with Stratus HLS

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine…

• less than a min read
High-Level Synthesis , webinars , TensorFlow , machine learning , Stratus , SystemC , HLS

Breakfast Bytes

PCIe Gen 4: It's Official, We're Compliant

Way back in April 2016, I wrote a post about Cadence IP for PCI Express (PCIe) Gen4…

• 3 min read
PCIe 4 , PCIe Gen4 , pcie 3

System, PCB, & Package Design 

IC Packagers: Capture Your Design for Review

How do you quickly show another developer an issue that concerns you? Do you need…

• 3 min read
APD , SiP Layout

Academic Network

Academic Network Engaging with National Taiwan University

The National Taiwan University hosted an EDA summer camp for the third consecutive…

• 3 min read
university , Student Day , Taiwan , Cadence Academic Network , academia , university program

Breakfast Bytes

MLPerf: Benchmarking Machine Learning

Most presentations at the recent HOT CHIPS conference are about actual chips, mostly…

• 6 min read

Analog/Custom Design

Virtuosity: Layout Reuse Flow in Modgen

Modgen now supports the Layout Reuse Flow. Read on to see how you can use this feature…

• 4 min read
Modgen On Canvas , ICADVM18.1 , MODGEN , Layout Suite , Layout , Virtuoso , Virtuosity , Layout design , Custom IC Design , modgens , Virtuoso Layout Suite , Custom IC

System, PCB, & Package Design 

DATA Pulse: Track Your Components—Efficient Library and Design Data Management

Ever noticed how some objects always mysteriously disappear? It's like they have…

• 1 min read
lifecycle , RAK , Allegro

Breakfast Bytes

Sunday Brunch Video for 15th September 2019

https://youtu.be/bcAO52jxk10 Made at SFO (camera Carey Guo) Monday: HOT CHIPS: In…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Ken的博客系列之六 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：高效的互连提取 使用IBIS-AMI模型进行仿真 此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型…

• less than a min read
PCB , SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , equalization , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性

Breakfast Bytes

Intelligent System Design

Yesterday in my post Intelligent Systems , I wrote about how the imperative for differentiated…

• 5 min read
system analysis , pervasive intelligence , design excellence , intelligent system design , system innovation

Breakfast Bytes

Intelligent Systems

Cadence's goal is to empower engineers at semiconductor and systems companies to…

• 4 min read
intelligent system design

Digital Design

Safety and Aging in IoT Devices: What We Know Today

How do we achieve highly accurate aging data models for critical circuits in automotive…

• 1 min read
iot devices , DAC 2019 , aging , GlobalFoundries

定制IC芯片设计

Virtuosity: Spring-Cleaned Virtuoso Doc Closet

如需了解IC6.1.8 和ICADVM18.1相关的最新文档，请继续阅读.

• less than a min read
legato , Chinese blog , Virtuoso Schematic Editor , ICADVM18.1 , Routing , ADE L , Virtuoso RF , Layout EXL , layout XL , Layout L , Cadence Help , Virtuoso Doc , Virtuoso Design Environment , New in EDA , Virtuoso Layout Suite EXL , IC6.1.8

Breakfast Bytes

EDPS Preview 2019

EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will…

• 3 min read
deep learning , 3DIC , EDPS , more than Moore , AI

Life at Cadence

How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and…

As we send off the last of our 2019 Summer Interns ( read more about their experience…

• 4 min read
intern , Student , internship

System, PCB, & Package Design 

IC Packagers: How Far Away are You?

Layout design is all about clearances. Daily challenges come from maintaining consistent…

• 3 min read
SiP Layout
CDNS - Fix Layout Hompage