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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed…

• 3 min read
real number modeling , AMS Designer , EDA training , SV-RNM , DMS , mixed signal , Schematic Model Generator , RAKs

Whiteboard Wednesdays

Whiteboard Wednesdays—Wireless Transceiver Implementations

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless…

• less than a min read
RF , wireless , Whiteboard Wednesdays , IP , 802.11x , digital , AFE , LTE

System, PCB, & Package Design 

What's Good About Allegro AMS Simulator PSpice Model Encryption? It’s in the 16.6…

With the 16.6 Allegro AMS Simulator (PSpice) release, you now have a new AES 256…

• less than a min read
AMS , Allegro 16.6 , AMS simulator , Allegro AMS , PSPICE , AMS simulation , model editor

Analog/Custom Design

What’s New in Virtuoso ADE XL in IC616 ISR6?

In a previous post, I explained the release model used for Virtuoso ADE and ViVA…

• 1 min read
Analog Design Environment , custom IC simulation , ADE XL , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Circuit Design , Custom IC Design , IC 6.1.6

RF Engineering

Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF

Hi All, Here's another great new feature that I've found very helpful... Broadband…

• less than a min read
nport , Spectre RF , Broadband SPICE , nport settings , Spectre , s parameter simulation

RF Engineering

New Memory Estimator Helps Determine Amount of Memory Required for Large Harmonic…

Hi Folks, A question that I've often received from designers, "Is there a method…

• 1 min read
HB , Spectre RF , MMSIM , spectreRF , harmonic balance , memory estimator

Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means…

• less than a min read
mobile devices , Whiteboard Wednesdays , D-PHY , MIPI protocols , MIPI PHYs

Analog/Custom Design

Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

Anyone who has ever played a musical instrument knows how hard it can be to keep…

• 4 min read
Variability Aware Design , ADE GXL , worst case corners , optimization , Virtuoso , statistical corners , Variation

Analog/Custom Design

Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

Highlights for this month include lots of useful Physical Verification System (PVS…

• 2 min read
Variability Aware Design , ADE GXL , Virtuoso , Analog Design Environment , PVS

System, PCB, & Package Design 

What's Good About Capture’s Auto Part Reference? 16.6 has a Few New Enhancements

The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered…

• less than a min read
capture , Cadence Design Systems , Allegro Design Entry , Design Entry CIS , cadence , Allegro Design Entry CIS , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , OrCAD , PCB design , Design Entry , Grzenia , PCB Capture , Schematic

Analog/Custom Design

What's New(-ish) in ADE XL in IC 616 ISR 3?

Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and…

• 1 min read
Analog Design Environment , ADE XL , Custom IC Design , IC 6.1.6

Whiteboard Wednesdays

Whiteboard Wednesdays - How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application…

• less than a min read
server virtualization , virtualization , IP , hosted virtual desktop , mobile workforces , BYOD

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits …

• 6 min read
IMC , low power simulation , uvm , Specman , LPS , x-propagation , RAK , incisive simulation , LSF , Glitches , state retention , drm , SystemC , vMananger , IES-XL

Digital Design

Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Friends, you would probably agree that sharing knowledge is a practical way to solve…

• 2 min read
EDI , Encounterer Digital Implementation System , Digital Implementation forums , Tempus , EDI system , Cadence Online Support , digital implementation , Digital Implementation , Encounter Digital Implementation , signoff , timing signoff

Verification

Applying Software-Driven Development Techniques to Testbench Development

Over the past couple of years there has been some interest in applying a software…

• 1 min read
AF , Specman , debug , e code , Funcional Verification , unit testing , Incisive Enterprise Simulator (IES)

System, PCB, & Package Design 

OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

• 1 min read
SiP , DDR interface , CDNLive , Co-Design , IC package design , OrbitIO

Whiteboard Wednesdays

Whiteboard Wednesdays - Comparing 3D Memory Solutions and Their Market Applicati…

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series…

• less than a min read
Whiteboard Wednesdays , 2D Memory , 3D memory , memory wall , SoC design

Analog/Custom Design

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic…

• 2 min read
ADE GXL , ADE XL , mismatch variation , Virtuoso Analog Design Environment , Monte Carlo , mismatch contribution analysis

Whiteboard Wednesdays

Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview…

• less than a min read
USB performance specs , Whiteboard Wednesdays , IP , USB 3.X , USB controllers , USB 2.0
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