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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Deque to the Rescue—Introducing the e Template Library

A customer working on a VIP component identified that the performance of one of their…

• 4 min read
e Template Library , e , FIFO , eTL , deque

System, PCB, & Package Design 

Optimize Complex Net Assignments Faster than Ever with Split Views in Cadence APD…

More differential pairs, larger buses, denser pin arrays… it’s no secret that IC…

• 2 min read
SiP , IC Package , IC Packaging , Allegro package design , SiP Design , Digital SiP design , IC Packaging and SiP , APD , IC Packaging & SiP design

Digital Design

Five-Minute Tutorial: Inserting Column Power Switches in EDI

Hello my fellow Digital Designers, I'm sorry I haven't been around the blogs much…

• 1 min read
EDI , Low Power , electronic system design , Cadence Online Support , Encounter Digital Implementation , five minute tutorial , power switch

Verification

Double-Take: Power Event Monitoring and In-Circuit Acceleration

For a number of years now, AMD has been applying an advanced acceleration use case…

• 1 min read
power event monitoring , Verification Computing Platform , system-level validation , hybrid verification , hardware assisted verification , Palladium XP , Emulation , in-circuit acceleration

SoC and IP

Looking Forward to MWC – Hope to See You There

This year’s Mobile World Congress (MWC) in Barcelona, March 2-5, should be the largest…

• 1 min read
DSP , IP , MIPI , Mobile World Congress , Tensilica , Tensilica IP , image processing , video processing , MWC 2015

Whiteboard Wednesdays

Whiteboard Wednesdays - Using the ARM AMBA Protocol

In this week's Whiteboard Wednesdays, Avi Behar follows up on his earlier video on…

• less than a min read
Whiteboard Wednesdays , IP , ARM AMBA , AMBA protocol , ARM

SoC and IP

Yes! Full 2-Day IP Track at CDNLive Silicon Valley

CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the…

• less than a min read
IP , DDR4 , CDNLive

SoC and IP

Increased CHI Coherency Verification Challenges

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface…

• 2 min read
Verification IP , Interconnect Validator , IVD , CHI , VIP , Dimitry Pavlovsky , Design IP and Verification IP , CHI VIP

Whiteboard Wednesdays

Whiteboard Wednesday—MIPI UniPro for Chip-to-Chip Communications

In this week's Whiteboard Wednesdays video, the last in a three-part series, Kevin…

• less than a min read
Whiteboard Wednesdays , IP , UniPro , communication protocol , MIPI

SoC and IP

Where’s My Star Trek Lifestyle?

The sparkle seems to have gone out of the Internet of Things (IoT) market for the…

• 2 min read
Smarthome , cadence , IP blocks , IoT , wearables , IP design , embedded design , robotics , embedded systems

Verification

Heading Off the Butterfly Effect—The SimVision "Quick Diff"

Functional Verification Debug Blog - SimVision Gems Most engineers are familiar…

• 1 min read
HDL , "butterfly effect" , SimVision waveforms diff , Verilog , SimCompare , VHDL

System, PCB, & Package Design 

What's Good About Using Allegro TimingVision and IPC-2581 to Reduce Design Costs…

This week, you can view a couple of videos where customers describe how they used…

• 1 min read
PCB Layout and routing , Allegro 16.6 , Routing , High Speed , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , DDR3

Analog/Custom Design

Virtuosity: 26 Things I Learned in November and December 2014 by Browsing Cadence…

Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena…

• 4 min read
Liberate AMS , MMSIM , ADE XL , ADE , Virtuoso , Spectre , Analog Design Environment , Virtuosity , PVS , Custom IC Design , Virtuoso Layout Suite , SKILL , IC 6.1.6

System, PCB, & Package Design 

What's Good About Using Sigrity to Gain Signal Access? Check Out This Expert Insights…

This week, you can view a video where a customer describes how they used the Cadence…

• less than a min read
SI , Cadence Design Systems , PCB Signal and power integrity , SPB , Signal Integrity , PCB Signal integrity , Grzenia , SI analysis and modeling

Whiteboard Wednesdays

Whiteboard Wednesdays—ARM AMBA Microcontroller Protocol Family

In this week's Whiteboard Wednesdays video, the first of a two-part series, Avi Behar…

• less than a min read
Whiteboard Wednesdays , CHI , ASB , ATB , APB , AMBA , ARM

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Thieving? 16.6 Has Several New Enhancements…

The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving…

• 1 min read
PCB Layout and routing , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

SoC and IP

HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF

High-performance and high-speed memory design characterized by low-power operation…

• 2 min read
DDR4 , electronic system design , cadence , IP blocks , TSMC , 16nm , FinFET , Hisilicon

SoC and IP

Cadence at CES 2015: Enabling Surreal Surround Sound Audio

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine…

• 1 min read
DTS , Consumer Electronics , cadence , surround sound , audio , Tensilica , HiFi DSP , CES 2015 , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Voltage and Monitoring IP

In this week's Whiteboard Wednesdays, Bob Salem discusses voltage and monitoring…

• less than a min read
IP , voltage and monitoring IP , temperature tracking , intellectual property
CDNS - Fix Layout Hompage